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ncv4269ad150r2g

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onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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NCV4269AD150R2G

onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

NCV4269AD150R2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I power_in Regulator input supply. Operating range 5.5 V to 45 V (5.0 V version), withstands +60 V transient and -40 V reverse. Connect to GND directly at the IC with a ceramic capacitor (typ. 0.1 μF to 470 nF).
2 SI input Sense Input to the on-chip voltage-monitor comparator. Typical threshold VSI,High = 1.31 V, VSI,Low = 1.20 V (bandgap-referenced); input current ±1 μA max. Drive from an external resistor divider off the monitored rail; if the sense function is not used, tie to Q.
3 RADJ input Reset Threshold Adjust. External resistor divider from Q to RADJ programs the reset trip point down from the default 4.65 V typ. to as low as 3.5 V (VRADJ,TH = 1.35 V typ.). Tie to GND when the adjustment function is not used to keep the default threshold.
4 D passive Reset Delay timing pin. Connect an external capacitor CD from D to GND to program the reset delay time td = CD·(VUD - VD,SAT)/ID,C (≈26 ms with 100 nF on the 5.0 V version, ID,C typ. 6.5 μA). Charges to VUD ≈1.8 V, discharges below VLD ≈0.45 V to assert reset.
5 GND power_in Device ground / signal return. All bypass capacitors reference this pin.
6 RO output Reset Output. Open-collector NPN with internal 20 kΩ (typ.) pull-up to Q; VRO,SAT ≤ 0.4 V. Driven low during power-up and any time VQ falls below VRT (4.65 V typ.) or the RADJ-programmed threshold; remains valid down to VQ = 1.0 V. Leave open if unused.
7 SO output Sense Output. Open-collector NPN with internal 20 kΩ (typ.) pull-up to Q; VSO,SAT ≤ 0.4 V. Goes low when SI drops below VSI,Low (1.20 V typ.) to give the microprocessor early warning of an impending reset. Leave open if unused.
8 Q power_out Regulated 5.0 V output (±2.0%) capable of 150 mA. Dropout 0.5 V max at 100 mA. Connect a 10 μF (min 2.2 μF) capacitor to GND with ESR < 10 Ω for stability; ceramic X7R (e.g. Murata GRM31CR71A106KA01) is acceptable with no minimum ESR.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

  • NCV4269AD150R2GD150G
  • NCV4269AD150R2G
  • NCV4269AD150R2GD133R2G
  • NCV4269AD150R2GPD50G
  • NCV4269AD150R2GPD50R2G
  • NCV4269AD150R2GD250G
  • NCV4269AD150R2GD250R2G
  • NCV4269AD150R2GDW50G
  • NCV4269AD150R2GDW50R2G

CAD (KiCad official)

  • Symbol: NCV4269AD150R2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncv4269ad150r2g-etched.step / ncv4269ad150r2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv4269ad150r2g.step / ncv4269ad150r2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 b38cb7c895a53288, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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Datasheet

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