component
NCP3420DR2G
Public Made by Adomby adom
onsemi Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7d ago |
| viewers | 7d ago |
| ncp3420dr2g-etched.glb | 7d ago |
| ncp3420dr2g-etched.step | 7d ago |
| ncp3420dr2g-hero.glb | 7d ago |
| ncp3420dr2g-hero.overlay.json | 7d ago |
| ncp3420dr2g.glb | 7d ago |
| ncp3420dr2g.kicad_mod | 7d ago |
| ncp3420dr2g.kicad_sym | 7d ago |
| ncp3420dr2g.lbr | 7d ago |
| ncp3420dr2g.step | 7d ago |
| package.json | 7d ago |
| page.json | 7d ago |
| README.md | 7d ago |
NCP3420DR2G
onsemi · Gate Drivers · SOIC-8
NCP3420DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | power_in | Upper MOSFET floating bootstrap supply; a capacitor between BST and SW holds the bootstrap voltage for the high-side MOSFET, with a recommended value between 100 nF and 1.0 µF, and an external diode is required. |
| 2 | IN | input | Logic-level PWM input with primary control of the drive outputs; input high requires at least 2.0 V and input low is 0.8 V maximum, with absolute maximum rating of 6.5 V. |
| 3 | OD | input | Output Disable input; when low, normal operation is disabled and DRVH and DRVL are forced low, with input high at least 2.0 V, input low at most 0.8 V, and absolute maximum rating of 6.5 V. |
| 4 | VCC | power_in | Input supply with a supply voltage range of 4.6 V to 13.2 V (absolute maximum 15 V), requiring a 1.0 µF ceramic capacitor from this pin to PGND. |
| 5 | DRVL | output | Output drive for the lower (low-side) MOSFET, referenced to PGND and powered from VCC. |
| 6 | PGND | power_in | Power ground, to be closely connected to the source of the lower MOSFET. |
| 7 | SWN | passive | Switch node, connected to the source of the upper MOSFET and serving as the bootstrap supply return; absolute maximum 35 V DC, 40 V for under 50 ns, and -5.0 V DC. |
| 8 | DRVH | output | Output drive for the upper (high-side) MOSFET, referenced to SW and powered from BST. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage Range | VCC | 4.6 | 13.2 | V | 4 | ||
| Supply Current | ISYS | 0.7 | 6 | mA | BST = 12 V, IN = 0 V | 4 | |
| OD Input Voltage High | VOD_HI | 2 | V | 4 | |||
| OD Input Voltage Low | VOD_LO | 0.8 | V | 4 | |||
| OD Propagation Delay Time (turn-off) | tpdlOD | 1 | 25 | 45 | ns | 4 | |
| OD Propagation Delay Time (turn-on) | tpdhOD | 1 | 25 | 45 | ns | 4 | |
| PWM Input Voltage High | VPWM_HI | 2 | V | 4 | |||
| PWM Input Voltage Low | VPWM_LO | 0.8 | V | 4 | |||
| OD Input Current | -1 | 1 | A | No internal pull-up or pull-down resistors | 4 | ||
| PWM Input Current | -1 | 1 | A | No internal pull-up or pull-down resistors | 4 | ||
| High-Side Driver Output Resistance, Sourcing Current | 1.8 | 3 | VBST − VSW = 12 V (Note 6) | 4 | |||
| High-Side Driver Output Resistance, Sinking Current | 1 | 2.5 | VBST − VSW = 12 V (Note 6) | 4 | |||
| SW Pulldown Resistance | 10 | 55 | k | SW to PGND | 4 | ||
| High-Side Driver Output Resistance, Unbiased | 10 | 55 | k | BST−SW = 0 V | 4 | ||
| High-Side Driver Transition Time (rise) | trDRVH | 16 | 30 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) | 4 | |
| High-Side Driver Transition Time (fall) | tfDRVH | 11 | 25 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) | 4 | |
| High-Side Driver Propagation Delay (Note 5), turn-on | tpdhDRVH | 20 | 30 | 45 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) | 4 |
| High-Side Driver Propagation Delay (Note 5), turn-off | tpdlDRVH | 10 | 30 | 45 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) | 4 |
| Low-Side Driver Output Resistance, Sourcing Current | 1.8 | 3 | VCC = 12 V (Note 6) | 4 | |||
| Low-Side Driver Output Resistance, Sinking Current | 1 | 2.5 | VCC − PGND = 12 V (Note 6) | 4 | |||
| Low-Side Driver Output Resistance, Unbiased | 10 | 55 | k | VCC = PGND | 4 | ||
| Low-Side Driver Transition Time (rise) | trDRVL | 16 | 30 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) | 4 | |
| Low-Side Driver Transition Time (fall) | tfDRVL | 11 | 25 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) | 4 | |
| Low-Side Driver Propagation Delay (Note 5), turn-on | tpdhDRVL | 15 | 30 | 45 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (Note 6, tpdhDRVL Only) (See Figure 3) | 4 |
| Low-Side Driver Propagation Delay (Note 5), turn-off | tpdlDRVL | 10 | 30 | 45 | ns | VBST − VSW = 12 V, CLOAD = 3.0 nF (See Figure 3) | 4 |
| UVLO Startup | 3.9 | 4.3 | 4.5 | V | 4 | ||
| UVLO Shutdown | 3.7 | 4.1 | 4.3 | V | 4 | ||
| UVLO Hysteresis | 0.1 | 0.2 | 0.4 | V | 4 | ||
| Over Temperature Protection (thermal shutdown) | 150 | 170 | °C | (Note 6) | 4 | ||
| Operating Ambient Temperature | TA | 0 | 85 | °C | 3 | ||
| Operating Junction Temperature | TJ | 0 | 150 | °C | Note 1 | 3 | |
| Storage Temperature Range | TS | -65 | 150 | °C | 3 | ||
| Lead Temperature Soldering (10 sec), Reflow Pb-Free | 260 | °C | Reflow (SMD styles only), Pb−Free (Note 3) | 3 | |||
| Main Supply Voltage Input | VCC | -0.3 | 15 | V | 3 | ||
| Bootstrap Supply Voltage Input (DC) | BST | 35 | V | DC wrt PGND | 3 | ||
| Bootstrap Supply Voltage Input (transient) | BST | 40 | V | < 50 ns wrt PGND | 3 | ||
| Bootstrap Supply Voltage Input (wrt SW) | BST | -0.3 | 15 | V | wrt SW | 3 | |
| Switching Node (DC) | SW | -5 | 35 | V | DC | 3 | |
| Switching Node (transient high) | SW | 40 | V | < 50 ns | 3 | ||
| Switching Node (transient low) | SW | -10 | V | < 200 ns | 3 | ||
| High-Side Driver Output (transient, wrt PGND) | DRVH | 35 | V | 50 ns wrt/PGND | 3 | ||
| High-Side Driver Output (wrt SW) | DRVH | -0.3 | 15 | V | wrt SW | 3 | |
| High-Side Driver Output (transient low, wrt SW) | DRVH | -2 | V | < 200 ns wrt SW | 3 | ||
| Low-Side Driver Output (DC) | DRVL | -0.3 | V | DC | 3 | ||
| Low-Side Driver Output (transient low) | DRVL | -5 | V | < 200 ns | 3 | ||
| IN Control Input | IN | -0.3 | 6.5 | V | 3 | ||
| OD Output Disable Input | OD | -0.3 | 6.5 | V | 3 | ||
| Package Thermal Resistance SO-8, Junction-to-Case | RJC | 45 | °C/W | 3 | |||
| Package Thermal Resistance SO-8, Junction-to-Ambient | RJA | 123 | °C/W | 2-Layer Board | 3 |
CAD (KiCad official)
- Symbol:
NCP3420DR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp3420dr2g-etched.step/ncp3420dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp3420dr2g.step/ncp3420dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (9 pp, sha256
ff86d43935c9d6be, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).