NCP1632DR2G

{
  "slug": "ncp1632dr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi AC-DC Controllers And Regulators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "ncp1632dr2g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ncp1632dr2g.kicad_sym",
    "ncp1632dr2g.kicad_mod",
    "ncp1632dr2g.glb",
    "ncp1632dr2g.step",
    "ncp1632dr2g.lbr",
    "docs/hero.png",
    "docs/ncp1632dr2g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ncp1632dr2g-hero.glb",
    "ncp1632dr2g-hero.overlay.json",
    "ncp1632dr2g-etched.glb"
  ],
  "component": {
    "mpn": "NCP1632DR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Power Management (PMIC)",
    "subcategory": "AC-DC Controllers And Regulators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908119515156480",
    "parts": {
      "symbol": "ncp1632dr2g.kicad_sym",
      "footprint": "ncp1632dr2g.kicad_mod",
      "model_3d": "ncp1632dr2g-hero.glb",
      "model_3d_plain": "ncp1632dr2g-etched.glb",
      "model_3d_step": "ncp1632dr2g-etched.step",
      "model_3d_step_plain": "ncp1632dr2g.step",
      "lbr": "ncp1632dr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C603642"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T23:06:54Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "ZCD2",
        "type": "input",
        "description": "Zero current detection input for phase 2 that monitors an auxiliary winding to detect inductor core reset and the MOSFET drain-source voltage valley, with a rising threshold of 0.50 V typical and an input clamp of 11 V typical at 5 mA."
      },
      {
        "number": "2",
        "name": "FB",
        "type": "input",
        "description": "Receives a portion of the PFC stage output voltage for regulation and is also monitored by the dynamic response enhancer, which speeds up loop response when the output voltage drops below 95.5 % of the set level."
      },
      {
        "number": "3",
        "name": "RT",
        "type": "passive",
        "description": "The resistor placed between this pin and ground sets the maximum on-time in both phases and therefore the maximum power the PFC stage can deliver."
      },
      {
        "number": "4",
        "name": "OSC",
        "type": "passive",
        "description": "Oscillator pin that sets the maximum switching frequency, particularly in medium- and light-load conditions when frequency foldback is engaged."
      },
      {
        "number": "5",
        "name": "VCONTROL",
        "type": "passive",
        "description": "Error amplifier output used for loop compensation, where the capacitor and resistor to ground set the regulation bandwidth, typically below 20 Hz, and the pin is grounded when the circuit is off for soft-start."
      },
      {
        "number": "6",
        "name": "FFOLD",
        "type": "passive",
        "description": "Sources a current proportional to the input current, and a resistor and capacitor from this pin to GND produce the voltage representing line current magnitude used for frequency foldback."
      },
      {
        "number": "7",
        "name": "BO",
        "type": "input",
        "description": "Brown-out input that receives an averaged portion of the input voltage; when VBO drops below 1 V (1.00 V typical threshold) the circuit stops pulsing after a 500 ms internal blanking delay and grounds the pfcOK pin."
      },
      {
        "number": "8",
        "name": "OVP / UVP",
        "type": "input",
        "description": "The circuit turns off when this pin falls below VUVP (300 mV typical) and disables the drive when it exceeds VOVP (2.5 V typical)."
      },
      {
        "number": "9",
        "name": "CS",
        "type": "input",
        "description": "Monitors a negative voltage proportional to the input current to limit the maximum current in the phases and to prevent start-up during large in-rush currents."
      },
      {
        "number": "10",
        "name": "Latch",
        "type": "input",
        "description": "Applying a voltage above VSTDWN (166 mV typical) latches the circuit off, and the device resets when the PFC stage is unplugged or when VCC falls below VCCRST (4 V typical)."
      },
      {
        "number": "11",
        "name": "DRV2",
        "type": "output",
        "description": "Totem-pole gate drive output for phase 2 of the interleaved PFC stage, with +0.5 / -0.8 A high-current capability for high gate charge MOSFETs."
      },
      {
        "number": "12",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply pin that starts operation when VCC exceeds 12 V, turns off below 10 V (typical), and has an operating range of 10.5 V to 20 V after start-up."
      },
      {
        "number": "13",
        "name": "GND",
        "type": "power_in",
        "description": "Connect this pin to the pre-converter ground."
      },
      {
        "number": "14",
        "name": "DRV1",
        "type": "output",
        "description": "Totem-pole gate drive output for phase 1 of the interleaved PFC stage, with +0.5 / -0.8 A high-current capability for high gate charge MOSFETs."
      },
      {
        "number": "15",
        "name": "REF5V / pfcOK",
        "type": "output",
        "description": "Outputs a 5 V typical reference that is high in steady state to signal the downstream converter that the PFC stage is ready, with a current capability of 5 mA minimum (10 mA typical)."
      },
      {
        "number": "16",
        "name": "ZCD1",
        "type": "input",
        "description": "Zero current detection input for phase 1 that monitors an auxiliary winding to detect inductor core reset and the MOSFET drain-source voltage valley, with a rising threshold of 0.50 V typical and an input clamp of 11 V typical at 5 mA."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: ERC types for RT, OSC, VCONTROL and FFOLD are judgment calls because the datasheet describes them as; REF5V/pfcOK is classed as output based on its 5 V reference and pfcOK signal function; the datasheet"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0694,
        "at": "2026-10-17T23:05:07"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908119515156480",
        "pages": 27,
        "sha256": "c6c004687695287d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ncp1632dr2g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ncp1632dr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "49ea9b8440e042806ea0bce2530d0151058e2fbd38869b0a665c6389fd6f3a1c",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}