# NCP1632DR2G

**onsemi** · AC-DC Controllers And Regulators · SOIC-16

NCP1632DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ZCD2 | input | Zero current detection input for phase 2 that monitors an auxiliary winding to detect inductor core reset and the MOSFET drain-source voltage valley, with a rising threshold of 0.50 V typical and an input clamp of 11 V typical at 5 mA. |
| 2 | FB | input | Receives a portion of the PFC stage output voltage for regulation and is also monitored by the dynamic response enhancer, which speeds up loop response when the output voltage drops below 95.5 % of the set level. |
| 3 | RT | passive | The resistor placed between this pin and ground sets the maximum on-time in both phases and therefore the maximum power the PFC stage can deliver. |
| 4 | OSC | passive | Oscillator pin that sets the maximum switching frequency, particularly in medium- and light-load conditions when frequency foldback is engaged. |
| 5 | VCONTROL | passive | Error amplifier output used for loop compensation, where the capacitor and resistor to ground set the regulation bandwidth, typically below 20 Hz, and the pin is grounded when the circuit is off for soft-start. |
| 6 | FFOLD | passive | Sources a current proportional to the input current, and a resistor and capacitor from this pin to GND produce the voltage representing line current magnitude used for frequency foldback. |
| 7 | BO | input | Brown-out input that receives an averaged portion of the input voltage; when VBO drops below 1 V (1.00 V typical threshold) the circuit stops pulsing after a 500 ms internal blanking delay and grounds the pfcOK pin. |
| 8 | OVP / UVP | input | The circuit turns off when this pin falls below VUVP (300 mV typical) and disables the drive when it exceeds VOVP (2.5 V typical). |
| 9 | CS | input | Monitors a negative voltage proportional to the input current to limit the maximum current in the phases and to prevent start-up during large in-rush currents. |
| 10 | Latch | input | Applying a voltage above VSTDWN (166 mV typical) latches the circuit off, and the device resets when the PFC stage is unplugged or when VCC falls below VCCRST (4 V typical). |
| 11 | DRV2 | output | Totem-pole gate drive output for phase 2 of the interleaved PFC stage, with +0.5 / -0.8 A high-current capability for high gate charge MOSFETs. |
| 12 | VCC | power_in | Positive supply pin that starts operation when VCC exceeds 12 V, turns off below 10 V (typical), and has an operating range of 10.5 V to 20 V after start-up. |
| 13 | GND | power_in | Connect this pin to the pre-converter ground. |
| 14 | DRV1 | output | Totem-pole gate drive output for phase 1 of the interleaved PFC stage, with +0.5 / -0.8 A high-current capability for high gate charge MOSFETs. |
| 15 | REF5V / pfcOK | output | Outputs a 5 V typical reference that is high in steady state to signal the downstream converter that the PFC stage is ready, with a current capability of 5 mA minimum (10 mA typical). |
| 16 | ZCD1 | input | Zero current detection input for phase 1 that monitors an auxiliary winding to detect inductor core reset and the MOSFET drain-source voltage valley, with a rising threshold of 0.50 V typical and an input clamp of 11 V typical at 5 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Power Supply Voltage (Continuous) | VCC(MAX) | -0.3 |  | 20 | V | Continuous | 2 |
| Maximum Input Voltage on Low Power Pins | VMAX | -0.3 |  | 9 | V | Pins 1, 2, 3, 4, 6, 7, 8, 9, 10, 15, 16 (Note 1) | 2 |
| VControl Pin Maximum Input Voltage | VControl(MAX) | -0.3 |  |  | V | Pin 5; upper limit printed as VControl(clamp) (Note 2), not a number | 2 |
| Maximum Power Dissipation | PD |  |  | 550 | mW | TA = 70°C | 2 |
| Operating Junction Temperature Range | TJ | -40 |  | 150 | °C |  | 2 |
| Maximum Junction Temperature | TJ(MAX) |  |  | 150 | °C |  | 2 |
| Storage Temperature Range | TS(MAX) | -65 |  | 150 | °C |  | 2 |
| Lead Temperature (Soldering) | TL(MAX) |  |  | 300 | °C | Soldering, 10s | 2 |
| ESD Capability, HBM model | ESD |  |  | 3 | kV | HBM model (Note 3) | 2 |
| ESD Capability, Machine Model | ESD |  |  | 200 | V | Machine Model (Note 3) | 2 |
| ESD Capability, Charged Device Model | ESD |  |  | 1000 | V | Charged Device Model (Note 3) | 2 |
| Supply Voltage operating range after start-up | VCC | 10.5 |  | 20 | V | After start-up | 7 |
| Startup Threshold (VCC increasing) | VCC(on) | 11 | 12 | 13 | V | VCC increasing | 4 |
| Minimum Operating Voltage (VCC decreasing) | VCC(off) | 9.4 | 10 | 10.4 | V | VCC decreasing | 4 |
| Hysteresis VCC(on) - VCC(off) | VCC(hyst) | 1.5 | 2 |  | V |  | 4 |
| Internal Logic Reset | VCC(reset) | 4 | 6 | 7.5 | V | VCC decreasing | 4 |
| Startup current | ICC(start) |  | 50 | 100 | µA | VCC = 9.4 V | 4 |
| Supply Current, device enabled/no output load on pin 6 | ICC1 |  | 3.5 | 7 | mA | Fsw = 130 kHz (Note 5) | 4 |
| Charge Current | ICH | 126 | 140 | 154 | µA | Pin 6 open | 4 |
| Maximum Discharge Current | IDISCH | 94.5 | 105 | 115.5 | µA | Pin 6 open | 4 |
| Pin 6 source current | IFFOLD30 | 28 | 30 | 32 | µA | ICS = 30 µA | 4 |
| Oscillator Lower Threshold | VOSC(low) | 3.6 | 4 | 4.4 | V | VFFOLD = 4.2 V, VFFOLD falling | 4 |
| Oscillator Lower Threshold | VOSC(low) | 2.7 | 3 | 3.3 | V | VFFOLD = 3.8 V, VFFOLD rising | 4 |
| Oscillator Lower Threshold | VOSC(low) | 1.8 | 2 | 2.2 | V | VFFOLD = 2.0 V, VFFOLD falling | 4 |
| Oscillator Lower Threshold | VOSC(low) | 0.8 | 1 | 1.1 | V | VFFOLD = 0.8 V, VFFOLD falling | 4 |
| Current Sense Voltage Offset | VCS(TH100) | -20 | 0 | 20 | mV | Ipin9 = 100 µA | 4 |
| Current Sense Protection Threshold | IILIM1 | 202 | 210 | 226 | µA | TJ = 25°C | 4 |
| Current Sense Protection Threshold | IILIM2 | 194 | 210 | 226 | µA | TJ = -40°C to 125°C | 4 |
| Threshold for In-rush Current Detection | Iin-rush | 11 | 14 | 17 | µA |  | 4 |
| Drive Resistance DRV1 Sink | RSNK1 |  | 7 | 15 | Ω | Ipin14 = 100 mA | 4 |
| Drive Resistance DRV1 Source | RSRC1 |  | 15 | 25 | Ω | Ipin14 = -100 mA | 4 |
| Feedback Voltage Reference | VREF | 2.44 | 2.5 | 2.56 | V |  | 5 |
| Error Amplifier Gain | GEA | 115 | 200 | 285 | S |  | 5 |
| Pin 5 Source Current when Vout(low) Detect is activated | IControl(boost) | 175 | 220 | 265 | µA | pfcOK high | 5 |
| Pin 5 Source Current when Vout(low) Detect is activated | IControl(boost) | 55 | 70 | 85 | µA | pfcOK low | 5 |
| Ratio Vout(low) Detect Threshold / VREF | Vout(low)/VREF | 95 | 95.5 | 96 | % | FB falling | 5 |
| Duty Cycle in skip mode | DMIN |  |  | 0 | % | VFB = 3 V | 5 |
| Maximum DRV1 and DRV2 On-Time | ton1 | 14.5 | 19.5 | 22.5 | µs | Vpin7 = 1.1 V, Ipin3 = 50 µA (Note 6) | 5 |
| Maximum DRV1 and DRV2 On-Time | ton2 | 1.1 | 1.35 | 1.6 | µs | Vpin7 = 1.1 V, Ipin3 = 200 µA | 5 |
| Maximum DRV1 and DRV2 On-Time | ton3 | 4 | 5 | 6 | µs | Vpin7 = 2.2 V, Ipin3 = 100 µA | 5 |
| Pin 3 voltage | VRt1 | 1.068 | 1.096 | 1.126 | V | VBO = Vpin7 = 1.1 V, Ipin3 = 50 µA | 5 |
| Pin 3 voltage | VRt3 | 2.165 | 2.196 | 2.228 | V | VBO = Vpin7 = 2.2 V, Ipin3 = 50 µA | 5 |
| Maximum Vton Voltage | Vton(MAX) |  |  | 5 | V | Not tested | 5 |
| Pin 3 Current Capability | IRt(MAX) | 1 |  |  | mA |  | 5 |
| ZCD Threshold Voltage (increasing) | VZCD(TH),H | 0.4 | 0.5 | 0.6 | V | VZCD increasing | 6 |
| ZCD Threshold Voltage (falling) | VZCD(TH),L | 0.2 | 0.25 | 0.3 | V | VZCD falling | 6 |
| Input Clamp Voltage High State | VZCD(high) | 9 | 11 | 13 | V | Ipin1 = 5.0 mA | 6 |
| Input Clamp Voltage Low State | VZCD(low) | -1.1 | -0.65 | -0.1 | V | Ipin1 = -5.0 mA | 6 |
| ZCD Watchdog Delay | tZCD | 80 | 200 | 320 | µs |  | 6 |
| Brown-Out Comparator Threshold | VBO(TH) | 0.97 | 1 | 1.03 | V |  | 6 |
| Brown-Out Current Source | IBO | 6 | 7 | 8 | µA |  | 6 |
| Brown-Out Blanking Time | tBO(BLANK) | 380 | 500 | 620 | ms |  | 6 |
| Pin BO voltage when clamped by the PNP | VBO(PNP) | 0.35 | 0.7 | 0.9 | V | Ipin7 = -100 µA | 6 |
| Over-Voltage Protection Threshold | VOVP | 2.425 | 2.5 | 2.575 | V |  | 6 |
| Ratio (VOVP / VREF) | VOVP/VREF | 99.2 | 99.7 | 100.2 | % |  | 6 |
| Pin Latch Threshold for Shutdown | VLatch | 140 | 166 | 200 | mV |  | 6 |
| Pin 15 Voltage High State | VREF5V(high) | 4.7 | 5 | 5.3 | V | Vpin7 = 0 V, Ipin15 = 5 mA | 6 |
| Thermal Shutdown Threshold | TSHDN | 130 | 140 | 150 | °C |  | 6 |
| Thermal Resistance Junction-to-Air | RJ-A |  | 145 |  | °C/W | Junction-to-Air | 2 |

## CAD (KiCad official)

- Symbol: `NCP1632DR2G`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `ncp1632dr2g-etched.step` / `ncp1632dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp1632dr2g.step` / `ncp1632dr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908119515156480) (27 pp, sha256 `c6c004687695287d`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ncp1632dr2g-datasheet.pdf)