# NCP1392BDR2G

**onsemi** · Gate Drive ICs · SOIC-8

NCP1392BDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supplies the driver; accepts up to 16 V given by the internal zener clamp (VCCclamp typ 16 V), with current into the pin limited to 20 mA max. |
| 2 | Rt | passive | Timing resistor connected between this pin and GND sets the operating frequency (25 kHz to 480 kHz); Rt pin reference voltage is 3.5 V and capacitance on the pin must be under 100 pF. |
| 3 | BO | input | Brown-out/enable input with 1 V brown-out level and 18.2 µA hysteresis current; on the B version, enable above Vref_EN (2 V) stops the driver and operation restores when it drops 100 mV below. |
| 4 | GND | power_in | IC ground. |
| 5 | Mlower | output | Low-side driver output that drives the lower side MOSFET, with output range -0.3 V to VCC + 0.3 V. |
| 6 | HB | passive | Half-bridge connection to the half-bridge output, rated -1 V to +600 V. |
| 7 | Mupper | output | High-side driver output that drives the higher side MOSFET, with output range Vbridge - 0.3 V to Vboot + 0.3 V. |
| 8 | Vboot | power_in | Bootstrap pin, the floating supply terminal for the upper stage, with Vboot-Vbridge rated 0 to 20 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Turn-On Threshold Level, VCC Going Up | VCCON | 10 | 11 | 12 | V | VCC = 12 V | 6 |
| Minimum Operating Voltage after Turn-On | VCCmin | 8 | 9 | 10 | V |  | 6 |
| Startup Voltage on the Floating Section | VbootON | 7.8 | 8.8 | 9.8 | V |  | 6 |
| Cutoff Voltage on the Floating Section | Vbootmin | 7 | 8 | 9 | V |  | 6 |
| Startup Current | ICC |  |  | 50 | µA | VCC < VCCON, 0°C ≤ Tamb ≤ +125°C | 6 |
| Startup Current | ICC |  |  | 65 | µA | VCC < VCCON, -40°C ≤ Tamb < 0°C | 6 |
| Consumption During PFC Delay Period | ICC4 |  |  | 400 | µA | 0°C ≤ Tamb ≤ +125°C | 6 |
| Consumption During PFC Delay Period | ICC4 |  |  | 470 | µA | -40°C ≤ Tamb < 0°C | 6 |
| VCC Zener Clamp Voltage | VCCclamp | 15.4 | 16 | 17.5 | V | @ 20 mA | 6 |
| Minimum Switching Frequency | FSW min | 24.25 | 25 | 25.75 | kHz | Rt = 35 k on Pin 2 for DT = 600 ns | 6 |
| Maximum Switching Frequency (B Version) | FSW maxB | 208 | 245 | 282 | kHz | Rt = 3.5 k on Pin 2, DT = 600 ns | 6 |
| Reference Voltage for all Current Generations | Vref RT | 3.33 | 3.5 | 3.67 | V |  | 6 |
| Operating Duty Cycle Symmetry | DC | 48 | 50 | 52 | % |  | 6 |
| Deadtime (B Version) | TdeadB | 540 | 610 | 720 | ns |  | 6 |
| Leakage Current on High Voltage Pins to GND | IHVLeak |  |  | 5 | µA | 600 Vdc | 6 |
| Brown-Out Level | VBO | 0.95 | 1 | 1.05 | V |  | 6 |
| Hysteresis Current | IBO | 15.6 | 18.2 | 20.7 | µA | Vpin3 < VBO | 6 |
| Reference Voltage for EN Input (B Version) | Vref EN | 1.9 | 2 | 2.1 | V |  | 6 |
| Temperature Shutdown | TSD | 140 |  |  | °C |  | 7 |
| Internal IC Consumption, No Output Load | ICC1 |  | 2.2 |  | mA | No Output Load on Pins 8/7 - 5/4, Fsw = 100 kHz | 6 |
| Internal IC Consumption, 1 nF Output Load | ICC2 |  | 3.4 |  | mA | 1 nF Output Load on Pins 8/7 - 5/4, Fsw = 100 kHz | 6 |
| Consumption in Fault Mode | ICC3 |  | 2.56 |  | mA | Drivers Disabled, VCC > VCC(min), RT = 3.5 k | 6 |
| Output Voltage Rise Time | Tr |  | 40 |  | ns | CL = 1 nF, 10-90% of Output Signal | 6 |
| Output Voltage Fall Time | Tf |  | 20 |  | ns | CL = 1 nF, 10-90% of Output Signal | 6 |
| Source Resistance | ROH |  | 12 |  | Ω |  | 6 |
| Sink Resistance | ROL |  | 5 |  | Ω |  | 6 |
| Delay Before Any Driver Restart (B Version) | PFC Delay |  | 100 |  | ms |  | 7 |
| Bridge Pin Voltage | Vbridge | -1 |  | 600 | V | Pin 6 | 5 |
| Floating Supply Voltage | Vboot - Vbridge | 0 |  | 20 | V |  | 5 |
| Allowable Output Slew Rate | dVbridge/dt |  |  | 50 | V/ns |  | 5 |
| Maximum Current into VCC Pin | ICC |  |  | 20 | mA | Pin 1, VBO = 0 V | 5 |
| Rt Pin Voltage | V_Rt | -0.3 |  | 5 | V |  | 5 |
| Maximum Voltage, All Pins (Except Pins 4 and 5) |  | -0.3 |  | 10 | V |  | 5 |
| Storage Temperature Range |  | -60 |  | 150 | °C |  | 5 |
| ESD Capability, HBM (All Pins Except HV Pins 6, 7 and 8) |  |  |  | 2 | kV | Human Body Model | 5 |
| ESD Capability, HBM (HV Pins 6, 7 and 8) |  |  |  | 1.5 | kV | Human Body Model | 5 |
| ESD Capability, Machine Model |  |  |  | 200 | V |  | 5 |
| Thermal Resistance Junction-to-Air | RθJA |  | 178 |  | °C/W | IC Soldered on 50 mm2 Copper 35 µm | 5 |
| Thermal Resistance Junction-to-Air | RθJA |  | 147 |  | °C/W | IC Soldered on 200 mm2 Copper 35 µm | 5 |

## CAD (KiCad official)

- Symbol: `NCP1392BDR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncp1392bdr2g-etched.step` / `ncp1392bdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp1392bdr2g.step` / `ncp1392bdr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp1392b-d.pdf) (21 pp, sha256 `dcd05630362c2867`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ncp1392bdr2g-datasheet.pdf)