component
NCL2801CDBDR2G
Public Made by Adomby adom
onsemi LED Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| docs | 9d ago |
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| ncl2801cdbdr2g-etched.step | 9d ago |
| ncl2801cdbdr2g-hero.glb | 9d ago |
| ncl2801cdbdr2g-hero.overlay.json | 9d ago |
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| ncl2801cdbdr2g.lbr | 9d ago |
| ncl2801cdbdr2g.step | 9d ago |
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| README.md | 9d ago |
NCL2801CDBDR2G
onsemi · LED Drivers · SOIC-8
NCL2801CDBDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Receives a portion of the PFC output voltage for regulation, DRE (below 95.5% of the desired output level), soft/fast OVP and UVP (UVP threshold VUVPH 450 mV typ); a 250-nA sink current disables the part if the pin is left open. |
| 2 | VCTRL | output | Error amplifier output where the external compensation network sets loop bandwidth below about 20 Hz; it is internally pulled down when the circuit is off for soft-start and must not be controlled or pulled down externally. |
| 3 | MULT | input | Multiplier input receiving a scaled-down rectified mains voltage from a resistor divider between Vin and GND; the controller is disabled if the pin is left open or exceeds Vmult_max (3.2 V typ). |
| 4 | CS | input | Senses the MOSFET current to end the on-time at the control value or the maximum current limit, and before startup senses the RCS resistance to GND to set the CrM-to-DCM VCTRL threshold. |
| 5 | ZCD | input | Uses the auxiliary winding voltage to detect the inductor current zero crossing, clamped at VCC plus a diode drop (max rating -0.3 V to VCC+0.3 V). |
| 6 | GND | power_in | Connect this pin to the PFC stage ground. |
| 7 | DRV | output | Totem-pole gate drive with -0.5 A/+0.8 A capability to drive high gate charge power MOSFETs. |
| 8 | VCC | power_in | Positive supply of the IC; for the C/D versions it starts at 12.5 V and turns off below 10.0 V (typ), operating range up to 27 V maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | LED Drivers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Start-Up Threshold, VCC increasing ([C] & [D] Versions) | VCC,on | 11.6 | 12.5 | 13.4 | V | VCC increasing; [C] & [D] Versions | 5 |
| Minimum Operating Voltage, VCC falling ([C] & [D] Versions) | VCC,off | 9.3 | 10 | 10.7 | V | VCC falling; [C] & [D] Versions | 5 |
| Voltage at which IC completely restarts | VCC,rst | 6.5 | 7.2 | 7.8 | V | ICC drops to ~ICC,start | 5 |
| Hysteresis (VCC,on − VCC,off) ([C] & [D] Versions) | VCC,hyst | 1.25 | 2.5 | 3.75 | V | [C] & [D] Versions | 5 |
| Start-Up Current | ICC,start | 0 | 10 | 60 | A | VCC = 9.4 V, below startup voltage | 5 |
| Operating Consumption, no switching | ICC,op1 | 0 | 0.4 | 1 | mA | no switching | 5 |
| Operating Consumption, 50-kHz switching | ICC,op2 | 1 | 2 | 3 | mA | 50-kHz switching, no load on DRV pin | 5 |
| Output voltage rise-time | tR | 15 | 30 | 90 | ns | CL = 1 nF, 10-90% of output signal | 5 |
| Output voltage fall-time | tF | 10 | 20 | 50 | ns | CL = 1 nF, 10-90% of output signal | 5 |
| Source resistance | ROH | 4 | 10 | 20 | @ 200 mV under High VCC | 5 | |
| Sink resistance | ROL | 2 | 7 | 15 | @ 200 mV above Low VCC | 5 | |
| DRV pin level for VCC = VCC,off + 200 mV ([C] & [D] Versions) | VDRV,low | 9.6 | 10 | 11 | V | 10-k resistor between DRV and GND; [C] & [D] Versions | 5 |
| DRV pin level at VCC = 27 V | VDRV,high | 10 | 12 | 14 | V | RL = 33 k & CL = 1 nF | 5 |
| Feedback Voltage Reference | VREF | 2.45 | 2.5 | 2.55 | V | 5 | |
| Error Amplifier Current Capability (source and sink) | IEA | 15 | 20 | 25 | A | source and sink | 5 |
| Error Amplifier Gain | GEA | 110 | 200 | 290 | S | 5 | |
| VCTRL pin Voltage (upper, Vctrl,max) | Vctrl,max | 4.4 | 4.5 | 4.6 | V | @ VFB = 2 V (OTA is sourcing 20 A) | 5 |
| VCTRL pin Voltage (lower, Vctrl,min) | Vctrl,min | 0.4 | 0.5 | 0.6 | V | @ VFB = 3 V (OTA is sinking 20 A) | 5 |
| Current Sense Voltage Reference (OCP), no line level detection | VCS_OCP(th) | 0.97 | 1.07 | 1.19 | V | [B]&[D] Options; at tLEB,OCP | 5 |
| Current Sense Overstress Voltage Reference, no line level detection | VCS_OVS(th) | 1.45 | 1.6 | 1.78 | V | [B]&[D] Options; at tLEB,OVS | 5 |
| Leading edge Blanking Time for current control | tLEB,OCP | 125 | 200 | 275 | ns | 6 | |
| Leading edge Blanking Time for Overstress | tLEB,OVS | 50 | 100 | 150 | ns | 6 | |
| Over-Current Protection Delay from VCS>VCS(th) to DRV low | tOCP | 10 | 40 | 200 | ns | VCS > VCS(th) + 100 mV | 6 |
| Watch Dog Timer in OverStress situation | tWDG(OS) | 400 | 800 | 1200 | s | 6 | |
| ZCD positive clamp | VCL(pos) | 12.6 | 12.9 | 13.2 | V | VCC = 12 V, IZCD = 5 mA | 6 |
| Zero Current Detection, VZCD rising | VZCD(th)H | 675 | 750 | 825 | mV | VZCD rising | 6 |
| Zero Current Detection, VZCD falling | VZCD(th)L | 200 | 250 | 300 | mV | VZCD falling | 6 |
| Hysteresis of the Zero Current Detection Comparator | VZCD(hyst) | 375 | 500 | 625 | mV | 6 | |
| ZCD pin input leakage current | IZCD,bias | 0 | 250 | 500 | nA | 6 | |
| Zero current detection to DRV high delay | tZCD | 20 | 80 | 200 | ns | (VZCD < VZCD(th)L) to (DRV high) | 6 |
| Multiplier Gain, no line level detection | Kmult | 0.34 | 0.38 | 0.42 | 1/V | [B]&[D] Options (w/o line level detection) | 6 |
| Koffset.Vton voltage added at the multiplier output, no line detection | Koffset_nld | 0.04 | 0.075 | 0.12 | [B]&[D] Options (w/o line detection) | 6 | |
| Maximum MULT pin voltage | Vmult_max | 2.88 | 3.2 | 3.52 | V | Controller disabled if MULT pin voltage goes above this threshold | 6 |
| Maximum on-time (high VCTRL) | tON,max,A,2 | 26 | 30 | 36 | s | @ VCTRL = 4.50 V | 6 |
| Maximum on-time (low VCTRL) | tON,max,A,1 | 3.6 | 5 | 6.9 | s | @ VCTRL = 0.55 V | 6 |
| Dead time added after 6th valley | tADT | 14 | 20 | s | Vctrl = 0.50 V | 8 | |
| Dead time added after 6th valley | tADT | 0 | 0.1 | 0.4 | s | Vctrl = 0.77 V | 8 |
| Ratio (Soft OVP Threshold, VFB rising) over VREF ([C**] Options) | RsoftOVP,C | 103.5 | 105 | 106.5 | % | Options [C**] | 8 |
| Ratio (Fast OVP Threshold, VFB rising) over VREF ([C**] Option) | RfastOVP,C | 103.2 | 107 | 110.8 | % | Option [C**] | 8 |
| Ratio (Fast OVP Hysteresis) over VREF | RfastOVP(HYST) | 3 | 4 | 5.7 | % | 8 | |
| FB pin pull-down Current | IB,FB | 50 | 200 | 450 | nA | VFB = VOVP and VFB = VUVP | 8 |
| Ratio (DRE Threshold, VFB falling) over VREF | RDRE | 94 | 95.7 | 97.5 | % | 8 | |
| Current measured out of VCTRL pin at startup (DRE) | IVCTRL,Startup | 80 | 100 | 120 | A | @ VFB=1V (PFCOK=0 ⇔ Startup) | 8 |
| Current measured out of VCTRL pin, steady state (DRE) | IVCTRL,1,Steady | 160 | 200 | 240 | A | @ VFB=1V (PFCOK=1 ⇔ Steady State); [B], [D], [F] Product Options | 8 |
| UVP Threshold, VFB increasing | VUVPH | 380 | 450 | 520 | mV | VFB increasing | 8 |
| UVP Threshold, VFB decreasing | VUVPL | 150 | 200 | 250 | mV | VFB decreasing | 8 |
| Thermal Shutdown Threshold | TLIMIT | 150 | °C | 9 | |||
| Operating supply range after start-up | VCC | 10 | 27 | V | After start-up; 9 V minimum for [A], [B], [E], [F] options | 3 | |
| Supply voltage input (absolute maximum) | VCC | -0.3 | 27 | V | 4 | ||
| FB pin rating | FB | -0.3 | 9 | V | 4 | ||
| VCTRL pin rating | VCTRL | -0.3 | V | Max is Vctrl,max, the VCTRL clamp voltage (Note 3) | 4 | ||
| MULT pin rating | MULT | -0.3 | 9 | V | 4 | ||
| CS pin rating | CS | -0.3 | 9 | V | 4 | ||
| ZCD pin rating | ZCD | -0.3 | V | Max is VCC+0.3 V | 4 | ||
| Driver voltage | VDRV | -0.3 | V | Max is VDRV (Note 3) | 4 | ||
| Driver current | IDRV | -500 | 800 | mA | 4 | ||
| Maximum Power Dissipation | PD | 300 | mW | @ TA = 70°C | 4 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 4 | ||
| Storage Temperature Range | TS,max | -65 | 150 | °C | 4 | ||
| Thermal Resistance Junction to Air | Rja | 180 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
NCL2801CDBDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncl2801cdbdr2g-etched.step/ncl2801cdbdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncl2801cdbdr2g.step/ncl2801cdbdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (28 pp, sha256
4746bd846f36d1af, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).