# NCD57080CDR2G

**onsemi** · Gate Drive ICs · SOIC-8

NCD57080CDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Input side power supply that needs a good quality bypass capacitor to GND1 placed close to the pin, with UVLO enabling operation when the supply is above VUVLO1-OUT-ON (absolute maximum 22 V). |
| 2 | IN+ | input | Non-inverted gate driver input, internally clamped to GND1 with an equivalent 125 kΩ pull-down resistor so the output is low with no input, and a minimum pulse width is required before OUTH/OUTL respond. |
| 3 | IN− | input | Inverted gate driver input, internally clamped to VDD1 with an equivalent 125 kΩ pull-up resistor so the output is low with no input, and a minimum pulse width is required before OUTH/OUTL respond. |
| 4 | GND1 | power_in | Input side ground reference. |
| 5 | VDD2 | power_in | Output side positive power supply, operating from the UVLO2 threshold up to its maximum (absolute maximum 32 V), needing a good quality bypass capacitor to GND2 placed close to the pin. |
| 6 | OUTH | output | Driver high output that provides the drive voltage and source current to the IGBT/MOSFET gate (6.5 A peak source). |
| 7 | OUTL | output | Driver low output that provides the drive voltage and sink current to the IGBT/MOSFET gate (6.5 A peak sink) and is actively pulled low during start-up. |
| 8 | GND2 | power_in | Output side gate drive reference connecting to the IGBT emitter or MOSFET source. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage, Input Side | VDD1-GND1 | -0.3 |  | 22 | V |  | 6 |
| Positive Power Supply, Output Side | VDD2-GND2 | -0.3 |  | 32 | V |  | 6 |
| Gate-driver Output Sourcing Current | IPK-SRC |  |  | 6.5 | A | max pulse width = 10 µs, max duty cycle = 0.2%, VDD2 = 15 V, VEE2 = 0 V | 6 |
| Gate-driver Output Sinking Current | IPK-SNK |  |  | 6.5 | A | max pulse width = 10 µs, max duty cycle = 0.2%, VDD2 = 15 V, VEE2 = 0 V | 6 |
| Maximum Short Circuit Clamping Time | tCLP |  |  | 10 | µs | IOUT_CLAMP = 500 mA | 6 |
| Power Dissipation (SOIC-8 Narrow) | PD |  |  | 1315 | mW |  | 6 |
| Maximum Junction Temperature | TJ(max) | -40 |  | 150 | °C |  | 7 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 7 |
| ESD Capability, Human Body Model | ESDHBM | -2 |  | 2 | kV |  | 7 |
| ESD Capability, Charged Device Model | ESDCDM | -2 |  | 2 | kV |  | 7 |
| Lead Temperature Soldering Reflow, Pb-Free | TSLD |  |  | 260 | °C |  | 7 |
| Supply Voltage, Input Side (operating max) | VDD1-GND1 |  |  | 20 | V |  | 7 |
| Positive Power Supply, Output Side (operating max) | VDD2-GND2 |  |  | 30 | V |  | 7 |
| Common Mode Transient Immunity | /dVISO/dt/ | 100 |  |  | kV/µs | tested by ±1500 V pulses up to 100 kV/µs | 7 |
| Ambient Temperature | TA | -40 |  | 125 | °C |  | 7 |
| Thermal Resistance, Junction-to-Air (4-Layer) | RθJA |  | 95 |  | °C/W | SOIC-8 narrow body, 100 mm2 1 oz copper, FR4 | 7 |
| Thermal Resistance, Junction-to-Air (1-Layer) | RθJA |  | 175 |  | °C/W | SOIC-8 narrow body, 100 mm2 1 oz copper, FR4 | 7 |
| UVLO1 Output Enabled | VUVLO1-OUT-ON |  |  | 3.1 | V |  | 8 |
| UVLO1 Output Disabled | VUVLO1-OUT-OFF | 2.4 |  |  | V |  | 8 |
| UVLO1 Hysteresis | VUVLO1-HYST | 0.1 |  |  | V |  | 8 |
| UVLO2 Output Enabled | VUVLO2-OUT-ON | 12.4 | 12.9 | 13.4 | V | NCx57080y | 8 |
| UVLO2 Output Disabled | VUVLO2-OUT-OFF | 11.5 | 12 | 12.5 | V | NCx57080y | 8 |
| UVLO2 Hysteresis | VUVLO2-HYST | 0.7 | 1 |  | V |  | 8 |
| Input Supply Quiescent Current | IDD1-0-3.3 |  |  | 2 | mA | IN+ = Low, IN- = Low, VDD1 = 3.3 V | 8 |
| Input Supply Current | IDD1-100-5 |  |  | 5.5 | mA | IN+ = High, IN- = Low | 8 |
| Output Positive Supply Quiescent Current | IDD2-0 |  |  | 2 | mA | IN+ = Low, IN- = Low, no load | 8 |
| Output Positive Supply Current | IDD2-100 |  |  | 2 | mA | IN+ = High, IN- = Low, no load | 8 |
| IN- Input Current | IIN-L-5 |  |  | 100 | µA | VIN- = 0 V | 8 |
| IN+ Input Current | IIN+H-5 |  |  | 100 | µA | VIN+ = VDD1 = 5 V | 8 |
| Input Pulse Width for Guaranteed No Response | tON-MIN1 |  |  | 10 | ns |  | 8 |
| Input Pulse Width for Guaranteed Response | tON-MIN2 | 40 |  |  | ns |  | 8 |
| Output Low State | VOUTL1 |  | 0.15 | 0.3 | V | ISINK = 200 mA | 9 |
| Output Low State | VOUTL2 |  |  | 0.8 | V | ISINK = 1.0 A, TA = 25°C | 9 |
| Output High State | VOUTH1 |  | 0.2 | 0.35 | V | ISRC = 200 mA | 9 |
| Output High State | VOUTH2 |  |  | 1 | V | ISRC = 1.0 A, TA = 25°C | 9 |
| Clamping Voltage, Sourcing | VCLAMP-OUTH |  | 0.7 | 1.3 | V | IN+ = Low, IN- = High, ICLAMP-OUT/OUTH = 500 mA | 9 |
| Clamping Voltage, Sinking | VCLAMP-OUTL |  | 0.8 | 1.5 | V | IN+ = High, IN- = Low, ICLAMP-OUTL = 500 mA | 9 |
| Propagation Delay to Output High | tPD-ON-3.3 | 40 | 60 | 90 | ns | VDD1 = VIN+ = 3.3V, VIN- = 0 V, CLOAD = 10 nF | 9 |
| Propagation Delay to Output Low | tPD-OFF-3.3 | 40 | 60 | 90 | ns | VDD1 = VIN+ = 3.3 V, VIN- = 0 V, CLOAD = 10 nF | 9 |
| Propagation Delay Distortion | tDISTORT | -25 |  | 25 | ns | TA = -40°C to 125°C, PW > 150 ns | 9 |
| Propagation Delay Distortion | tDISTORT |  | 0 |  | ns | TA = 25°C, PW > 150 ns | 9 |
| Prop Delay Distortion between Parts | tDISTORT_TOT | -30 | 0 | 30 | ns | PW > 150 ns | 9 |
| Rise Time | tRISE |  | 13 |  | ns | CLOAD = 1 nF, 10% to 90% of Output Change | 9 |
| Fall Time | tFALL |  | 13 |  | ns | CLOAD = 1 nF, 90% to 10% of Output Change | 9 |
| Peak Driver Current, Sink | IPK-SNK1 |  | 6.5 |  | A |  | 9 |
| Peak Driver Current, Source | IPK-SRC1 |  | 6.5 |  | A |  | 9 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | ABS |  | RIO Insulation Resistance at TS, VIO = 500 V 109 Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) | 6 |

## CAD (KiCad official)

- Symbol: `NCD57080CDR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncd57080cdr2g-etched.step` / `ncd57080cdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncd57080cdr2g.step` / `ncd57080cdr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncd57080c-d.pdf) (24 pp, sha256 `748b3eca1fc6dfa7`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ncd57080cdr2g-datasheet.pdf)