NCD57080BDR2G

{
  "slug": "ncd57080bdr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management ics",
    "ncd57080bdr2g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ncd57080bdr2g.kicad_sym",
    "ncd57080bdr2g.kicad_mod",
    "ncd57080bdr2g.glb",
    "ncd57080bdr2g.step",
    "ncd57080bdr2g.lbr",
    "docs/hero.png",
    "docs/ncd57080bdr2g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ncd57080bdr2g-hero.glb",
    "ncd57080bdr2g-hero.overlay.json",
    "ncd57080bdr2g-etched.glb"
  ],
  "component": {
    "mpn": "NCD57080BDR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Power Management ICs",
    "subcategory": "Gate Drive ICs",
    "datasheet": "https://www.onsemi.com/pdf/datasheet/ncd57080b-d.pdf",
    "parts": {
      "symbol": "ncd57080bdr2g.kicad_sym",
      "footprint": "ncd57080bdr2g.kicad_mod",
      "model_3d": "ncd57080bdr2g-hero.glb",
      "model_3d_plain": "ncd57080bdr2g-etched.glb",
      "model_3d_step": "ncd57080bdr2g-etched.step",
      "model_3d_step_plain": "ncd57080bdr2g.step",
      "lbr": "ncd57080bdr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C2902052",
      "digikey": "488-NCD57080BDR2GTR-ND",
      "mouser": "863-NCD57080BDR2G"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T17:22:14Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "488-NCD57080BDR2GTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "863-NCD57080BDR2G",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD1",
        "type": "power_in",
        "description": "Input-side power supply; a good quality bypass capacitor is required from this pin to GND1, placed close to the pins, and the UVLO circuit enables operation at power-on when a typical supply above VUVLO1-OUT-ON is present."
      },
      {
        "number": "2",
        "name": "IN+",
        "type": "input",
        "description": "Non-inverting gate driver input, internally clamped to GND1 with an equivalent 125 kΩ pull-down to keep the output low without an input signal, and a minimum positive or negative pulse width is required before OUT responds."
      },
      {
        "number": "3",
        "name": "IN−",
        "type": "input",
        "description": "Inverting gate driver input, internally clamped to VDD1 with an equivalent 125 kΩ pull-up to keep the output low without an input signal, and a minimum positive or negative pulse width is required before OUT responds."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Input-side ground reference."
      },
      {
        "number": "5",
        "name": "VDD2",
        "type": "power_in",
        "description": "Output-side positive power supply whose operating range runs from UVLO2 to its maximum allowed value; a good quality bypass capacitor is required from this pin to GND2, placed close to the pins."
      },
      {
        "number": "6",
        "name": "OUT",
        "type": "output",
        "description": "Driver output that provides the drive voltage and source/sink current to the IGBT/MOSFET gate, rated for 6.5 A peak sourcing and 6.5 A peak sinking (pulsed), and is actively pulled low during start-up."
      },
      {
        "number": "7",
        "name": "GND2",
        "type": "power_in",
        "description": "Output-side gate drive reference connected to the IGBT emitter or MOSFET source (pin 7 on version B; pin 8 on versions A and C)."
      },
      {
        "number": "8",
        "name": "VEE2",
        "type": "power_in",
        "description": "Output-side negative power supply with a good quality bypass capacitor required from this pin to GND2 placed close to the pin; VEE2-GND2 is rated from -18 V to 0.3 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin assignment for the B version (NCx5708zB, which includes NCD57080BDR2G) differs from versions A a; Table 1 gives the UVLO thresholds only by reference to Figures 9A-9D, which are not in the excerpt, "
        ],
        "pages_sent": 10,
        "cost_usd": 0.0596,
        "at": "2026-10-30T17:21:59"
      },
      "datasheet": {
        "url": "https://www.onsemi.com/pdf/datasheet/ncd57080b-d.pdf",
        "pages": 24,
        "sha256": "748b3eca1fc6dfa7",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ncd57080bdr2g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ncd57080bdr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "335bdde23e9d9ac293c5dc72e26ccaf0bbc48fa8156fc8d72abf4c7d37bfaa32",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "SOIC-8 NB (CASE 751-07)",
      "source_page": 22,
      "D": {
        "nom_mm": 4.9,
        "range_mm": [
          4.8,
          5.0
        ]
      },
      "E1": {
        "nom_mm": 3.9,
        "range_mm": [
          3.8,
          4.0
        ]
      },
      "E": {
        "nom_mm": 6.0,
        "range_mm": [
          5.8,
          6.2
        ]
      },
      "e": {
        "nom_mm": 1.27,
        "range_mm": [
          null,
          null
        ]
      },
      "A": {
        "nom_mm": 1.55,
        "range_mm": [
          1.35,
          1.75
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "ncd57080bdr2g.step",
        "verdict": "PASS",
        "reasons": [
          "height and body within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}