N32G4FRHEQ7

{
  "slug": "n32g4frheq7",
  "version": "0.1.0",
  "type": "component",
  "description": "Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "n32g4frheq7",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "n32g4frheq7.kicad_sym",
    "n32g4frheq7.kicad_mod",
    "n32g4frheq7.glb",
    "n32g4frheq7.step",
    "n32g4frheq7.lbr",
    "docs/hero.png",
    "docs/n32g4frheq7-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "n32g4frheq7-hero.glb",
    "n32g4frheq7-hero.overlay.json",
    "n32g4frheq7-etched.glb"
  ],
  "component": {
    "mpn": "N32G4FRHEQ7",
    "manufacturer": "Nations Technologies Inc",
    "package": "QFN-40-EP(5x5)",
    "pin_count": 41,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588894491919200256",
    "parts": {
      "symbol": "n32g4frheq7.kicad_sym",
      "footprint": "n32g4frheq7.kicad_mod",
      "model_3d": "n32g4frheq7-hero.glb",
      "model_3d_plain": "n32g4frheq7-etched.glb",
      "model_3d_step": "n32g4frheq7-etched.step",
      "model_3d_step_plain": "n32g4frheq7.step",
      "lbr": "n32g4frheq7.lbr"
    },
    "distributor_links": {
      "lcsc": "C2828612"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T18:11:10Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "PC14-OSC32_IN",
        "type": "bidirectional",
        "description": "PC14 is an I/O on the backup power switch limited to about 3 mA, so as an output it may only work at 2 MHz with up to 30 pF load and cannot source current such as driving an LED; its alternate function is OSC32_IN for the 32.768 kHz LSE oscillator."
      },
      {
        "number": "2",
        "name": "PC15-OSC32_OUT",
        "type": "bidirectional",
        "description": "PC15 is an I/O on the same limited backup power switch (about 3 mA, one output at a time, 2 MHz, 30 pF max, no current sourcing), and its alternate function is OSC32_OUT for the 32.768 kHz LSE oscillator."
      },
      {
        "number": "3",
        "name": "OSC_IN",
        "type": "input",
        "description": "HSE oscillator input for a 4-32 MHz crystal/resonator or external clock (table level TC, pin shown as OSC_IN in Table 3-1)."
      },
      {
        "number": "4",
        "name": "OSC_OUT",
        "type": "output",
        "description": "HSE oscillator output for a 4-32 MHz crystal/resonator (table level TC)."
      },
      {
        "number": "5",
        "name": "NRST",
        "type": "input",
        "description": "Active-low external reset input with an internal pull-up resistor (20-50 kΩ), where pulses shorter than 100 ns are filtered and pulses longer than 300 ns are not filtered."
      },
      {
        "number": "6",
        "name": "VSSA",
        "type": "power_in",
        "description": "Analog ground for the ADC, DAC, reset block, RC oscillators and PLL, which must be connected to VSS."
      },
      {
        "number": "7",
        "name": "VDDA",
        "type": "power_in",
        "description": "Analog supply for the ADC, DAC, reset block, RC oscillators and PLL, rated 1.8-3.6 V and required to be the same as VDD (at most 300 mV difference during power-up and operation)."
      },
      {
        "number": "8",
        "name": "PA0-WKUP",
        "type": "bidirectional",
        "description": "PA0 is a TTa-level I/O (not marked 5 V tolerant) whose default function is PA0 with WKUP wake-up and ADC1_IN1, and whose alternates include USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and SPI3_MISO."
      },
      {
        "number": "9",
        "name": "PA1",
        "type": "bidirectional",
        "description": "PA1 is a TTa-level I/O (not 5 V tolerant) with ADC1_IN2 as default function and alternates USART2_RTS, TIM5_CH2, TIM2_CH2, DVP_HSYNC, SPI3_MOSI and I2S3_SD."
      },
      {
        "number": "10",
        "name": "PA2",
        "type": "bidirectional",
        "description": "PA2 is a TTa-level I/O (not 5 V tolerant) with alternates USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3 and DVP_VSYNC."
      },
      {
        "number": "11",
        "name": "PA3",
        "type": "bidirectional",
        "description": "PA3 is a TTa-level I/O (not 5 V tolerant) with alternates USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4 and DVP_PCLK."
      },
      {
        "number": "12",
        "name": "VDD_4",
        "type": "power_in",
        "description": "Digital supply pin (1.8-3.6 V) that powers the I/O pins and the internal voltage regulator."
      },
      {
        "number": "13",
        "name": "PA4",
        "type": "bidirectional",
        "description": "PA4 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, DVP_D0, QSPI_NSS, TSC_CHN0 and I2C2_SCL."
      },
      {
        "number": "14",
        "name": "PA5",
        "type": "bidirectional",
        "description": "PA5 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_SCK, DAC_OUT2, ADC2_IN2, DVP_D1, QSPI_SCK, TSC_CHN1 and I2C2_SDA."
      },
      {
        "number": "15",
        "name": "PA6",
        "type": "bidirectional",
        "description": "PA6 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, DVP_D2, QSPI_IO0 and TIM1_BKIN."
      },
      {
        "number": "16",
        "name": "PA7",
        "type": "bidirectional",
        "description": "PA7 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, DVP_D3, QSPI_IO1 and TIM1_CH1N."
      },
      {
        "number": "17",
        "name": "PC4",
        "type": "bidirectional",
        "description": "PC4 is a TTa-level I/O (not 5 V tolerant) with alternates ADC2_IN5, DVP_D4, QSPI_IO2, UART7_TX and I2C3_SCL."
      },
      {
        "number": "18",
        "name": "PC5",
        "type": "bidirectional",
        "description": "PC5 is a TTa-level I/O (not 5 V tolerant) with alternates ADC2_IN12, DVP_D5, QSPI_IO3, UART7_RX and I2C3_SDA."
      },
      {
        "number": "19",
        "name": "PB0",
        "type": "bidirectional",
        "description": "PB0 is a TTa-level I/O (not 5 V tolerant) with alternates TIM3_CH3, TIM8_CH2N, DVP_D6, TIM1_CH2N and UART6_TX."
      },
      {
        "number": "20",
        "name": "PB1",
        "type": "bidirectional",
        "description": "PB1 is a TTa-level I/O (not 5 V tolerant) with alternates ADC2_IN3, TIM3_CH4, TIM8_CH3N, DVP_D7, TIM1_CH3N and UART6_RX."
      },
      {
        "number": "21",
        "name": "PB12",
        "type": "bidirectional",
        "description": "PB12 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN and CAN2_RX."
      },
      {
        "number": "22",
        "name": "PB13",
        "type": "bidirectional",
        "description": "PB13 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and UART5_TX."
      },
      {
        "number": "23",
        "name": "PB14",
        "type": "bidirectional",
        "description": "PB14 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_MISO, TIM1_CH2N, USART3_RTS, TSC_CHN2 and UART5_RX."
      },
      {
        "number": "24",
        "name": "PB15",
        "type": "bidirectional",
        "description": "PB15 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_MOSI, I2S2_SD, TIM1_CH3N and TSC_CHN3."
      },
      {
        "number": "25",
        "name": "PA8",
        "type": "bidirectional",
        "description": "PA8 is a 5 V tolerant (FT) I/O with alternates USART1_CK, TIM1_CH1 and MCO."
      },
      {
        "number": "26",
        "name": "PA9",
        "type": "bidirectional",
        "description": "PA9 is a 5 V tolerant (FT) I/O with alternates USART1_TX, TIM1_CH2, TSC_DOUT and I2C4_SCL."
      },
      {
        "number": "27",
        "name": "PA10",
        "type": "bidirectional",
        "description": "PA10 is a 5 V tolerant (FT) I/O with alternates USART1_RX, TIM1_CH3, I2C4_SDA and XFMC_MWE."
      },
      {
        "number": "28",
        "name": "PA11",
        "type": "bidirectional",
        "description": "PA11 is a 5 V tolerant (FT) I/O with alternates USART1_CTS, USBDM, CAN1_RX and TIM1_CH4."
      },
      {
        "number": "29",
        "name": "PA12",
        "type": "bidirectional",
        "description": "PA12 is a 5 V tolerant (FT) I/O with alternates USART1_RTS, USBDP, CAN1_TX and TIM1_ETR."
      },
      {
        "number": "30",
        "name": "PA13",
        "type": "bidirectional",
        "description": "PA13 is a 5 V tolerant (FT) I/O whose default function is JTMS-SWDIO (SWD debug data), with alternate UART4_TX."
      },
      {
        "number": "31",
        "name": "VDD_2",
        "type": "power_in",
        "description": "Digital supply pin (1.8-3.6 V) that powers the I/O pins and the internal voltage regulator."
      },
      {
        "number": "32",
        "name": "PA14",
        "type": "bidirectional",
        "description": "PA14 is a 5 V tolerant (FT) I/O whose default function is JTCK-SWCLK (SWD clock), with alternate UART4_RX."
      },
      {
        "number": "33",
        "name": "PA15",
        "type": "bidirectional",
        "description": "PA15 is a 5 V tolerant (FT) I/O whose default function is JTDI, with alternates SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS and TIM8_CH1N."
      },
      {
        "number": "34",
        "name": "PB3",
        "type": "bidirectional",
        "description": "PB3 is a 5 V tolerant (FT) I/O whose default function is JTDO, with alternates TRACESWO, SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK, USART2_RTS and TIM8_BKIN."
      },
      {
        "number": "35",
        "name": "PB4",
        "type": "bidirectional",
        "description": "PB4 is a 5 V tolerant (FT) I/O whose default function is NJTRST, with alternates SPI3_MISO, TIM3_CH1, SPI1_MISO, USART2_TX and TIM8_ETR."
      },
      {
        "number": "36",
        "name": "PB5",
        "type": "bidirectional",
        "description": "PB5 is a 5 V tolerant (FT) I/O with alternates I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX and TIM1_BKIN."
      },
      {
        "number": "37",
        "name": "PB6",
        "type": "bidirectional",
        "description": "PB6 is a TTa-level I/O (not 5 V tolerant) with alternates I2C1_SCL, TIM4_CH1, TSC_CHN20, USART1_TX, CAN2_TX, XFMC_NE2 and XFMC_NCE3."
      },
      {
        "number": "38",
        "name": "BOOT0",
        "type": "input",
        "description": "Boot mode select input which, together with BOOT1, selects boot from main Flash, system memory or internal SRAM, and which has an internal input pull-down."
      },
      {
        "number": "39",
        "name": "VSS_3",
        "type": "power_in",
        "description": "Ground pin for the digital supply and I/O circuits, which must be connected to the system ground."
      },
      {
        "number": "40",
        "name": "VDD_3",
        "type": "power_in",
        "description": "Digital supply pin (1.8-3.6 V) that powers the I/O pins and internal regulator; the 4.7 µF decoupling capacitor must be connected to VDD3 per the power-scheme note."
      },
      {
        "number": "41",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package mapping not stated explicitly in the provided text: the ordering code for N32G4FRHEQ7 (the '; Exposed thermal pad (the 'EP' in the package hint) is not described or numbered anywhere in the prov; Inconsistent OSC pin references: Table 3-1 places OSC_IN on QFN40 pin 3 and OSC_OUT on pin 4, but fo",
          "exposed pad 41 added from the footprint"
        ],
        "pages_sent": 66,
        "cost_usd": 0.2972,
        "at": "2026-10-18T18:10:53"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588894491919200256",
        "pages": 85,
        "sha256": "67b1cccbf08f5d1a",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 41,
        "described": 41,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "n32g4frheq7.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          5.0,
          5.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "8f37bc7a9aab4742c34f137d9822c0352acc227532830034555744338483cdfc",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "n32g4frheq7-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "1dd92b7abcbfe29ccce26da36dcf7f90ff291c624299347b2fc03ee1b3998546",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}