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N32G4FRHEQ7

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Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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N32G4FRHEQ7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · QFN-40-EP(5x5)

N32G4FRHEQ7 from Nations Technologies Inc, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC14-OSC32_IN bidirectional PC14 is an I/O on the backup power switch limited to about 3 mA, so as an output it may only work at 2 MHz with up to 30 pF load and cannot source current such as driving an LED; its alternate function is OSC32_IN for the 32.768 kHz LSE oscillator.
2 PC15-OSC32_OUT bidirectional PC15 is an I/O on the same limited backup power switch (about 3 mA, one output at a time, 2 MHz, 30 pF max, no current sourcing), and its alternate function is OSC32_OUT for the 32.768 kHz LSE oscillator.
3 OSC_IN input HSE oscillator input for a 4-32 MHz crystal/resonator or external clock (table level TC, pin shown as OSC_IN in Table 3-1).
4 OSC_OUT output HSE oscillator output for a 4-32 MHz crystal/resonator (table level TC).
5 NRST input Active-low external reset input with an internal pull-up resistor (20-50 kΩ), where pulses shorter than 100 ns are filtered and pulses longer than 300 ns are not filtered.
6 VSSA power_in Analog ground for the ADC, DAC, reset block, RC oscillators and PLL, which must be connected to VSS.
7 VDDA power_in Analog supply for the ADC, DAC, reset block, RC oscillators and PLL, rated 1.8-3.6 V and required to be the same as VDD (at most 300 mV difference during power-up and operation).
8 PA0-WKUP bidirectional PA0 is a TTa-level I/O (not marked 5 V tolerant) whose default function is PA0 with WKUP wake-up and ADC1_IN1, and whose alternates include USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and SPI3_MISO.
9 PA1 bidirectional PA1 is a TTa-level I/O (not 5 V tolerant) with ADC1_IN2 as default function and alternates USART2_RTS, TIM5_CH2, TIM2_CH2, DVP_HSYNC, SPI3_MOSI and I2S3_SD.
10 PA2 bidirectional PA2 is a TTa-level I/O (not 5 V tolerant) with alternates USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3 and DVP_VSYNC.
11 PA3 bidirectional PA3 is a TTa-level I/O (not 5 V tolerant) with alternates USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4 and DVP_PCLK.
12 VDD_4 power_in Digital supply pin (1.8-3.6 V) that powers the I/O pins and the internal voltage regulator.
13 PA4 bidirectional PA4 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, DVP_D0, QSPI_NSS, TSC_CHN0 and I2C2_SCL.
14 PA5 bidirectional PA5 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_SCK, DAC_OUT2, ADC2_IN2, DVP_D1, QSPI_SCK, TSC_CHN1 and I2C2_SDA.
15 PA6 bidirectional PA6 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, DVP_D2, QSPI_IO0 and TIM1_BKIN.
16 PA7 bidirectional PA7 is a TTa-level I/O (not 5 V tolerant) with alternates SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, DVP_D3, QSPI_IO1 and TIM1_CH1N.
17 PC4 bidirectional PC4 is a TTa-level I/O (not 5 V tolerant) with alternates ADC2_IN5, DVP_D4, QSPI_IO2, UART7_TX and I2C3_SCL.
18 PC5 bidirectional PC5 is a TTa-level I/O (not 5 V tolerant) with alternates ADC2_IN12, DVP_D5, QSPI_IO3, UART7_RX and I2C3_SDA.
19 PB0 bidirectional PB0 is a TTa-level I/O (not 5 V tolerant) with alternates TIM3_CH3, TIM8_CH2N, DVP_D6, TIM1_CH2N and UART6_TX.
20 PB1 bidirectional PB1 is a TTa-level I/O (not 5 V tolerant) with alternates ADC2_IN3, TIM3_CH4, TIM8_CH3N, DVP_D7, TIM1_CH3N and UART6_RX.
21 PB12 bidirectional PB12 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN and CAN2_RX.
22 PB13 bidirectional PB13 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and UART5_TX.
23 PB14 bidirectional PB14 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_MISO, TIM1_CH2N, USART3_RTS, TSC_CHN2 and UART5_RX.
24 PB15 bidirectional PB15 is a TTa-level I/O (not 5 V tolerant) with alternates SPI2_MOSI, I2S2_SD, TIM1_CH3N and TSC_CHN3.
25 PA8 bidirectional PA8 is a 5 V tolerant (FT) I/O with alternates USART1_CK, TIM1_CH1 and MCO.
26 PA9 bidirectional PA9 is a 5 V tolerant (FT) I/O with alternates USART1_TX, TIM1_CH2, TSC_DOUT and I2C4_SCL.
27 PA10 bidirectional PA10 is a 5 V tolerant (FT) I/O with alternates USART1_RX, TIM1_CH3, I2C4_SDA and XFMC_MWE.
28 PA11 bidirectional PA11 is a 5 V tolerant (FT) I/O with alternates USART1_CTS, USBDM, CAN1_RX and TIM1_CH4.
29 PA12 bidirectional PA12 is a 5 V tolerant (FT) I/O with alternates USART1_RTS, USBDP, CAN1_TX and TIM1_ETR.
30 PA13 bidirectional PA13 is a 5 V tolerant (FT) I/O whose default function is JTMS-SWDIO (SWD debug data), with alternate UART4_TX.
31 VDD_2 power_in Digital supply pin (1.8-3.6 V) that powers the I/O pins and the internal voltage regulator.
32 PA14 bidirectional PA14 is a 5 V tolerant (FT) I/O whose default function is JTCK-SWCLK (SWD clock), with alternate UART4_RX.
33 PA15 bidirectional PA15 is a 5 V tolerant (FT) I/O whose default function is JTDI, with alternates SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS and TIM8_CH1N.
34 PB3 bidirectional PB3 is a 5 V tolerant (FT) I/O whose default function is JTDO, with alternates TRACESWO, SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK, USART2_RTS and TIM8_BKIN.
35 PB4 bidirectional PB4 is a 5 V tolerant (FT) I/O whose default function is NJTRST, with alternates SPI3_MISO, TIM3_CH1, SPI1_MISO, USART2_TX and TIM8_ETR.
36 PB5 bidirectional PB5 is a 5 V tolerant (FT) I/O with alternates I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX and TIM1_BKIN.
37 PB6 bidirectional PB6 is a TTa-level I/O (not 5 V tolerant) with alternates I2C1_SCL, TIM4_CH1, TSC_CHN20, USART1_TX, CAN2_TX, XFMC_NE2 and XFMC_NCE3.
38 BOOT0 input Boot mode select input which, together with BOOT1, selects boot from main Flash, system memory or internal SRAM, and which has an internal input pull-down.
39 VSS_3 power_in Ground pin for the digital supply and I/O circuits, which must be connected to the system ground.
40 VDD_3 power_in Digital supply pin (1.8-3.6 V) that powers the I/O pins and internal regulator; the 4.7 µF decoupling capacitor must be connected to VDD3 per the power-scheme note.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package QFN-40-EP(5x5)
Category Embedded Processors & Controllers
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Clock frequency in data transfer mode fPP 0 48 MHz CL ≤ 30pF 74
Clock low time tW(CKL) 32 ns fPP = 16 MHz, CL ≤ 30pF 74
Clock high time tW(CKH) 30 ns CL ≤ 30pF 74
SD clock rise time tr 6 ns CL ≤ 30pF 74
SD clock fall time tf 6 ns CL ≤ 30pF 74
Input setup time (CMD, D inputs, referenced to CK) tISU 2 ns CL ≤ 30pF 74
Input hold time (CMD, D inputs, referenced to CK) tIH 2 ns CL ≤ 30pF 74
Output valid time, MMC and SD high-speed mode (CMD, D outputs, referenced to CK) tOV 14 ns CL ≤ 30pF 74
Output hold time, MMC and SD high-speed mode (CMD, D outputs, referenced to CK) tOH 2.5 ns CL ≤ 30pF 74
Output valid default time, SD default mode (CMD, D outputs, referenced to CK) tOVD 9 ns CL ≤ 30pF 75
Output hold default time, SD default mode (CMD, D outputs, referenced to CK) tOHD -2 ns CL ≤ 30pF 75
USB operating voltage VDD 3 3.6 V 75
Static output high level VOH 2.8 3.6 V 15kΩ load RL to VSS 75
Static output low level VOL 0.3 V 1.5kΩ load RL to 3.6V 75
Differential input sensitivity VDI 0.2 V I(USBDP，USBDM) 75
Differential common-mode range VCM 0.8 2.5 V includes VDI range 75
Single-ended receiver threshold VSE 1.3 2 V 75
USB full-speed rise time tr 4 20 ns CL ≤ 50pF 75
USB full-speed fall time tf 4 20 ns CL ≤ 50pF 75
Rise/fall time matching (tr/tf) trfm 90 110 % 75
Output signal crossover voltage VCRS 1.3 2 V 75
Output series matching resistance Rs 27 39 Ohm external matching resistor placed close to chip pin 76
USB transceiver startup time tSTARTUP 1 μs 75
ADC supply voltage VDDA 1.8 3.6 V 76
ADC positive reference voltage VREF+ 1.8 V 76
ADC clock frequency fADC 72 MHz 76
ADC sampling rate fs 5 MHz 76
ADC conversion voltage range VAIN 0 V VSSA or VREF- connected to ground 76
ADC sampling switch resistance RADC 600 kΩ 76
ADC internal sampling and hold capacitance CADC 5 pF 76
ADC sampling time tS 1.5 239.5 1/fADC 76
ADC power-up time tSTAB 0 0 20 μs 76
ADC total conversion time (including sampling time) tCONV 14 252 1/fADC sampling tS + successive approximation 12.5 76
ADC total error (ET) ET -5 1.3 5 LSB fHCLK = 72 MHz, fADC = 72 MHz, sample rate = 1.75 Msps, VDDA = 3.3V, TA = 25 °C, measured after ADC calibration, VREF+ = VDDA 76
ADC offset error (EO) EO -2 1 2 LSB 76
ADC differential linearity error (ED) ED -1 0.7 1 LSB 76
ADC integral linearity error (EL) EL -2 0.8 2 LSB 76
ADC signal to noise and distortion ratio SNDR 65 dBFS 76
ADC calibration time Tcal 82 1/fADC 76

CAD (KiCad official)

  • Symbol: N32G4FRHEQ7
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: n32g4frheq7-etched.step / n32g4frheq7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32g4frheq7.step / n32g4frheq7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (85 pp, sha256 67b1cccbf08f5d1a, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF