component

N32G435KBL7

Public Made by Adom

by adom

Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersn32g435kbl7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers n32g435kbl7: viewers · Ray 7d ago
n32g435kbl7-etched.glb Publish 0.1.0 · Ray 7d ago
n32g435kbl7-etched.step n32g435kbl7: factory component page (tier=lcsc) · Ray 7d ago
n32g435kbl7-hero.glb n32g435kbl7: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
n32g435kbl7-hero.overlay.json Publish 0.1.0 · Ray 7d ago
n32g435kbl7.glb Publish 0.1.0 · Ray 7d ago
n32g435kbl7.kicad_mod Publish 0.1.0 · Ray 7d ago
n32g435kbl7.kicad_sym Publish 0.1.0 · Ray 7d ago
n32g435kbl7.lbr Publish 0.1.0 · Ray 7d ago
n32g435kbl7.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

N32G435KBL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

N32G435KBL7 from Nations Technologies Inc, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply for the I/O pins and internal voltage regulator, 1.8 V to 3.6 V.
2 PD14-OSC_IN bidirectional GPIO PD14 (TTa 3.3 V I/O, not fail-safe) that also serves as the HSE oscillator input OSC_IN; alternates include USART2_TX, I2C2_SDA and TIM1_CH3N.
3 PD15-OSC_OUT bidirectional GPIO PD15 (TTa 3.3 V I/O, not fail-safe) that also serves as the HSE oscillator output OSC_OUT; alternates include USART2_RX and I2C2_SCL.
4 NRST input Active-low external reset input with internal pull-up of 30 to 70 kΩ (50 kΩ typ. at 3.3 V); pulses shorter than 100 ns are filtered.
5 VDDA/VREF+ power_in Analog supply for the ADC, DAC, OPAMP and COMP at 1.8 V to 3.6 V, which must be connected to VDD; also the ADC/DAC positive reference.
6 PA0 bidirectional GPIO PA0 (TTa 3.3 V I/O, fail-safe supported); default analog ADC_IN1 with alternates including TIM2_CH1, SPI1_MISO and WKUP1 wake-up.
7 PA1 bidirectional GPIO PA1 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN2 and OPAMP1_VINP, with alternates including USART2_RTS, LPUART_TX and TIM5_CH2.
8 PA2 bidirectional GPIO PA2 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN3 and OPAMP1_VOUT, with alternates including USART2_TX, TIM5_CH3, I2C2_SDA and COMP2_OUT.
9 PA3 bidirectional GPIO PA3 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN4 and OPAMP1_VINM, with alternates including USART2_RX, LPUART_RX, TIM5_CH4 and I2C2_SCL.
10 PA4 bidirectional GPIO PA4 (TTa 3.3 V I/O, not fail-safe); analog DAC_OUT and ADC_IN5, with alternates including USART2_CK, SPI1_NSS, I2S1_WS and I2C1_SCL.
11 PA5 bidirectional GPIO PA5 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN6, with alternates including SPI1_SCK, I2S1_CK, I2C1_SDA and USART1_RX.
12 PA6 bidirectional GPIO PA6 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN7 and OPAMP2_VOUT, with alternates including SPI1_MISO, I2S1_MCK, TIM3_CH1 and TIM1_BKIN.
13 PA7 bidirectional GPIO PA7 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN8, with alternates including SPI1_MOSI, I2S1_SD, TIM3_CH2 and TIM1_CH1N.
14 PB0 bidirectional GPIO PB0 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN9 and OPAMP2_VINM, with alternates including TIM1_CH2N, TIM3_CH3 and UART4_TX.
15 PB1 bidirectional GPIO PB1 (TTa 3.3 V I/O, fail-safe supported); analog ADC_IN10, with alternates including LPUART_RTS, TIM1_CH3N, TIM3_CH4 and UART4_RX.
16 VSS power_in Ground reference (0 V) for the digital core and I/O.
17 VDD power_in Power supply for the I/O pins and internal voltage regulator, 1.8 V to 3.6 V.
18 PA8 bidirectional GPIO PA8 (TTa 3.3 V I/O, fail-safe supported); alternates include USART1_CK, TIM1_CH1, I2C2_SMBA, MCO and the WKUP0 wake-up input.
19 PA9 bidirectional GPIO PA9 (TTa 3.3 V I/O, fail-safe supported); alternates include USART1_TX, I2C2_SCL and TIM1_CH2.
20 PA10 bidirectional GPIO PA10 (TTa 3.3 V I/O, fail-safe supported); alternates include USART1_RX, I2C2_SDA, SPI1_SCK, I2S1_CK and TIM1_CH3.
21 PA11 bidirectional GPIO PA11 (TTa 3.3 V I/O, not fail-safe); alternates include USART1_CTS, CAN_RX, TIM1_CH4 and COMP1_OUT, and it also serves as USB_DM.
22 PA12 bidirectional GPIO PA12 (TTa 3.3 V I/O, not fail-safe); alternates include USART1_RTS, CAN_TX, TIM1_ETR and COMP2_OUT, and it also serves as USB_DP.
23 PA13 bidirectional GPIO PA13 (TTa 3.3 V I/O, fail-safe supported); default SWDIO/JTMS debug function after reset, with alternates SPI2_NSS and I2S2_WS.
24 PA14 bidirectional GPIO PA14 (TTa 3.3 V I/O, fail-safe supported); default SWCLK/JTCK debug function after reset, with alternates USART2_CK, I2C1_SDA and COMP2_OUT.
25 PA15 bidirectional GPIO PA15 (TTa 3.3 V I/O, fail-safe supported); default JTDI debug function (pull-up after reset), with alternates USART2_CTS, SPI2_NSS, I2S2_WS and TIM2_CH1.
26 PB3 bidirectional GPIO PB3 (TTa 3.3 V I/O, fail-safe supported); default JTDO/TRACESWO debug function, with alternates USART2_RTS, SPI1_SCK, I2S1_CK and TIM2_CH2.
27 PB4 bidirectional GPIO PB4 (TTa 3.3 V I/O, fail-safe supported); default NJTRST debug function, with alternates USART2_TX, SPI1_MISO, TIM3_CH1 and UART5_TX.
28 PB5 bidirectional GPIO PB5 (TTa 3.3 V I/O, fail-safe supported); alternates include USART2_RX, I2C1_SMBA, SPI1_MOSI, I2S1_SD, TIM3_CH2 and LPTIM_IN1.
29 PB6 bidirectional GPIO PB6 (TTa 3.3 V I/O, fail-safe supported); alternates include USART1_TX, LPUART_TX, I2C1_SCL, SPI1_NSS, TIM4_CH1 and LPTIM_ETR.
30 PB7 bidirectional GPIO PB7 (TTa 3.3 V I/O, fail-safe supported); alternates include USART1_RX, LPUART_RX, I2C1_SDA, TIM4_CH2, LPTIM_IN2 and PVD_IN.
31 BOOT0/PD0 bidirectional Boot mode select input BOOT0 (input pull-down, sampled at reset) that can also be used as GPIO PD0 (TTa 3.3 V I/O, fail-safe supported).
32 VSS power_in Ground reference (0 V) for the digital core and I/O.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output low-level voltage, VDD 3.3 V VOL 0.4 V VDD = 3.3 V, IOL = 2mA, 4mA, 8mA, and 12mA 54
Output low-level voltage, VDD 2.5 V VOL 0.4 V VDD = 2.5 V, IOL = 1.5mA, 3mA, 7mA, and 11mA 54
Output high-level voltage, VDD 3.3 V VOH 2.4 V VDD = 3.3 V, IOH = -2mA, -4mA, -8mA, and -12mA 54
Output high-level voltage, VDD 2.5 V VOH 2 V VDD = 2.5 V, IOH = -1.5mA, -3mA, -7mA, and -11mA 54
NRST input high-level voltage VIH(NRST) 2 V VDD = 3.3 V 56
NRST Schmitt trigger hysteresis Vhys(NRST) 200 mV VDD = 3.3 V 56
NRST weak pull-up equivalent resistance RPU 30 50 70 KΩ VDD = 3.3 V 56
NRST input filtered pulse VF(NRST) 100 ns 56
NRST input non-filtered pulse VNF(NRST) 300 ns 56
I/O max frequency, 2mA drive (config 00) fmax(IO)out 75 MHz CL = 5pF, VDD = 3.3V 55
I/O max frequency, 4mA drive (config 10) fmax(IO)out 90 MHz CL = 10pF, VDD = 3.3V 55
I/O max frequency, 8mA drive (config 01) fmax(IO)out 75 MHz CL = 20pF, VDD = 3.3V 55
I/O max frequency, 12mA drive (config 11) fmax(IO)out 75 MHz CL = 30pF, VDD = 3.3V 55
I/O output delay, 2mA drive (config 00) t(IO)out 3.66 ns CL = 5pF, VDD = 3.3V 55
I/O output delay, 4mA drive (config 10) t(IO)out 3.5 ns CL = 10pF, VDD = 3.3V 55
I/O output delay, 8mA drive (config 01) t(IO)out 3.42 ns CL = 20pF, VDD = 3.3V 55
I/O output delay, 12mA drive (config 11) t(IO)out 3.34 ns CL = 30pF, VDD = 3.3V 55
I/O input delay (config 00) t(IO)in 1.2 ns CL = 50fF, VDD = 2.97V, VDDD = 0.81V 55
I/O input delay (config 10) t(IO)in 1.2 ns CL = 50fF, VDD = 2.97V, VDDD = 0.81V 55
I/O input delay (config 01) t(IO)in 1.2 ns CL = 50fF, VDD = 2.97V, VDDD = 0.81V 55
I/O input delay (config 11) t(IO)in 1.2 ns CL = 50fF, VDD = 2.97V, VDDD = 0.81V 55
Timer resolution time (TIM1/8) tres(TIM) 1 tTIMCLK 57
Timer resolution time (TIM1/8), fTIMCLK 108 MHz tres(TIM) 9.259 ns fTIMCLK = 108MHz 57
Timer external clock frequency (TIM1/8), fTIMCLK 108 MHz fEXT 0 54 MHz fTIMCLK = 108MHz 57
Timer resolution (TIM1/8) ResTIM 16 bits 57
16-bit counter clock period (TIM1/8) tCOUNTER 1 65536 tTIMCLK 57
16-bit counter clock period (TIM1/8), fTIMCLK 108 MHz tCOUNTER 0.009259 606.815 μs fTIMCLK = 108MHz 57
Maximum possible count (TIM1/8), fTIMCLK 108 MHz tMAX_COUNT 39.768 s fTIMCLK = 108MHz 57
Timer resolution time (TIM2-7/9), fTIMCLK 54 MHz tres(TIM) 18.519 ns fTIMCLK = 54MHz 57
Timer external clock frequency (TIM2-7/9), fTIMCLK 54 MHz fEXT 0 27 MHz fTIMCLK = 54MHz 57
Timer resolution (TIM2-7/9) ResTIM 16 bits 57
16-bit counter clock period (TIM2-7/9), fTIMCLK 54 MHz tCOUNTER 0.0185185 1213.63 μs fTIMCLK = 54MHz 57
Maximum possible count (TIM2-7/9), fTIMCLK 54 MHz tMAX_COUNT 79.536 s fTIMCLK = 54MHz 57
LPTIM timer resolution time, fLPTIMCLK 27 MHz tres(LPTIM) 37.037 ns fLPTIMCLK = 27MHz 57
LPTIM external clock frequency, fLPTIMCLK 27 MHz fEXT 0 27 MHz fLPTIMCLK = 27MHz 57
LPTIM timer resolution ResLPTIM 16 bits 57
LPTIM 16-bit counter clock period, fLPTIMCLK 27 MHz tCOUNTER 0.037037 2427.26 μs fLPTIMCLK = 27MHz 57
LPTIM maximum possible count, fLPTIMCLK 27 MHz tMAX_COUNT 159.073 s fLPTIMCLK = 27MHz 57
I2C interface frequency, standard mode fSCL 0 100 KHz Standard mode 58
I2C interface frequency, fast mode fSCL 0 400 KHz Fast mode 58
I2C interface frequency, fast-mode plus fSCL 0 1000 KHz Fast-mode plus 58
SPI clock frequency, master mode fSCLK 27 MHz Master mode 59
SPI clock frequency, slave mode fSCLK 27 MHz Slave mode 59
USB transceiver startup time tSTARTUP 1 μs 63
USB operating voltage VDD 3 3.6 V 64
USB differential input sensitivity VDI 0.2 V I (USBDP和USBDM) 64
USB differential common-mode range VCM 0.8 2.5 V 包含VDI范围 64
USB single-ended receiver threshold VSE 1.3 2 V 64
USB static output low level VOL 0.3 V 1.5KΩ RL接3.6V 64
USB static output high level VOH 2.8 3.6 V 15KΩ RL接VSS 64
USB full-speed rise time tr 4 20 ns CL ≤ 50pF 64
USB full-speed fall time tf 4 20 ns CL ≤ 50pF 64
USB rise/fall time matching trfm 90 111.1 % tr / tf 64
ADC supply voltage VDDA 1.8 3.6 V 使用外部参考电压 64
ADC clock frequency fADC 72 MHz 65
ADC sampling rate, 12-bit resolution fs 0.01 5.14 MHz 分辨率12-bit 65
ADC power-up time tSTAB 6 10 20 μs 65
ADC internal sample and hold capacitance CADC 5 pF 65
ADC signal-to-noise and distortion ratio SNDR 65 dBFS 65
Operating temperature range, grade 7 (ordering code N32G435KBL7) -40 105 ℃ 84

CAD (KiCad official)

  • Symbol: N32G435KBL7
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: n32g435kbl7-etched.step / n32g435kbl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32g435kbl7.step / n32g435kbl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (88 pp, sha256 be3b80dd8e09ff8d, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF