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MSPM0G3107SRHBR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0G3107SRHBR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32(5x5)

MSPM0G3107SRHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5 V tolerant open-drain general-purpose I/O (UART0_TX, I2C0_SDA, FCC_IN, among others) that can wake the device from SHUTDOWN; an external pull-up is required for output high.
2 PA1 bidirectional 5 V tolerant open-drain general-purpose I/O (UART0_RX, I2C0_SCL, among others) that can wake the device from SHUTDOWN; an external pull-up is required for output high.
3 NRST input Active-low reset input that must be pulled up to VDD for the device to leave reset and start; TI recommends a 47 kΩ pull-up with a 10 nF capacitor.
4 VDD power_in Device supply voltage, recommended range 1.62 V to 3.6 V (absolute maximum -0.3 V to 4.1 V), with a 10 µF and 0.1 µF low-ESR decoupling capacitor pair placed close to the pin.
5 VSS power_in Ground supply pin for the device, to which the VDD decoupling capacitors and the VCORE capacitor return.
6 PA2 bidirectional General-purpose digital I/O that is also the ROSC pin; when the SYSOSC frequency correction loop is used, a 100 kΩ ±0.1% (±25 ppm) resistor must be connected from this pin to VSS.
7 PA3 bidirectional Standard-drive general-purpose I/O that also serves as the LFXT low-frequency crystal input (LFXIN, 32.768 kHz).
8 PA4 bidirectional Standard-drive general-purpose I/O that also serves as the LFXT crystal output (LFXOUT) or the digital LFCLK_IN input (29.491 kHz to 36.045 kHz).
9 PA5 bidirectional Standard-drive general-purpose I/O that also serves as the HFXT high-frequency crystal input (HFXIN, 4 MHz to 48 MHz depending on HFXTRSEL) and FCC_IN.
10 PA6 bidirectional Standard-drive general-purpose I/O that also serves as the HFXT crystal output (HFXOUT) or the digital HFCLK_IN input (4 MHz to 48 MHz).
11 PA7 bidirectional Standard-drive general-purpose digital I/O that can also be configured as a clock output (CLK_OUT) and timer channels.
12 PA8 bidirectional Standard-drive general-purpose digital I/O with UART1, SPI0, UART0 and TIMA alternate functions.
13 PA9 bidirectional High-speed general-purpose digital I/O (HSIO) with UART1, SPI0, RTC_OUT and CLK_OUT alternate functions; output frequency up to 40 MHz at DRV=1 with VDD ≥ 2.7 V and 20 pF load.
14 PA10 bidirectional High-drive general-purpose I/O (HDIO) that can wake the device from SHUTDOWN, with an absolute maximum sink or source current of 20 mA.
15 PA11 bidirectional High-drive general-purpose I/O (HDIO) that can wake the device from SHUTDOWN, with an absolute maximum sink or source current of 20 mA.
16 PA12 bidirectional High-speed general-purpose digital I/O with UART3, SPI0, CAN_TX, TIMG0 and FCC_IN alternate functions.
17 PA13 bidirectional High-speed general-purpose digital I/O with UART3, SPI0, CAN_RX, TIMG0 and TIMA0 alternate functions.
18 PA14 bidirectional High-speed general-purpose digital I/O that also serves as ADC0 analog input channel 12 (A0_12), with UART0, SPI0, UART3 and CLK_OUT alternate functions.
19 PA15 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC1 analog input channel 0 (A1_0), with UART0, SPI1, I2C1 and timer alternate functions.
20 PA16 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC1 analog input channel 1 (A1_1), with SPI1, I2C1, timer and FCC_IN alternate functions.
21 PA17 bidirectional Standard-drive general-purpose digital I/O with shutdown wake-up capability that also serves as ADC1 analog input channel 2 (A1_2), with UART1, SPI1 and I2C1 alternate functions.
22 PA18 bidirectional Standard-drive general-purpose digital I/O with shutdown wake-up capability that also serves as ADC1 analog input channel 3 (A1_3) and the GPAMP inverting input (GPAMP_IN-).
23 PA19 bidirectional High-speed general-purpose I/O that carries the serial wire debug data signal SWDIO (bidirectional, shared).
24 PA20 input Standard-drive general-purpose I/O that carries the serial wire debug clock input SWCLK from the debug probe.
25 PA21 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC1 analog input channel 7 (A1_7) and the VREF- external reference or ground pin.
26 PA22 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC0 analog input channel 7 (A0_7) and the GPAMP output (GPAMP_OUT).
27 PA23 bidirectional Standard-drive general-purpose digital I/O that also serves as the VREF+ voltage reference pin, for external reference input or internal reference output, which requires a decoupling capacitor (0.7 µF to 1.15 µF) to VREF-/GND.
28 PA24 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC0 analog input channel 3 (A0_3), with UART2, SPI0 and timer alternate functions.
29 PA25 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC0 analog input channel 2 (A0_2), with UART3, SPI1 and timer alternate functions.
30 PA26 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC0 analog input channel 1 (A0_1) and the GPAMP non-inverting input (GPAMP_IN+).
31 PA27 bidirectional Standard-drive general-purpose digital I/O that also serves as ADC0 analog input channel 0 (A0_0) and the RTC clock output (RTC_OUT).
32 VCORE power_out Regulated core supply output; a 0.47 µF capacitor must be connected close to the device between VCORE and VSS, and no external voltage or load may be applied to this pin.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: MSPM0G3107SRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: mspm0g3107srhbr-etched.step / mspm0g3107srhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g3107srhbr.step / mspm0g3107srhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (69 pp, sha256 7c5df909316e74bc, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF