component
MSPM0G3106SRHBR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MSPM0G3106SRHBR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32(5x5)
MSPM0G3106SRHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA0 | bidirectional | General-purpose digital I/O pin configurable as UART0_TX, I2C0_SDA, TIMA0_C0, timer output, or FCC input with 5V tolerant open-drain capability. |
| 2 | PA1 | bidirectional | General-purpose digital I/O pin configurable as UART0_RX, I2C0_SCL, TIMA0_C1, timer input/output, or FCC input with 5V tolerant open-drain capability. |
| 3 | NRST | input | Reset input signal, active low; must be pulled high to VDD for device operation. |
| 4 | VDD | power_in | Main power supply voltage input, 1.62V to 3.6V recommended operating range. |
| 5 | VSS | power_in | Ground/reference voltage for power supply. |
| 6 | PA2/ROSC | bidirectional | General-purpose digital I/O or external precision resistor input for SYSOSC frequency correction loop when FCL is enabled. |
| 7 | PA3/LFXIN | bidirectional | Low-frequency crystal oscillator input or general-purpose digital I/O pin with standard drive capability. |
| 8 | PA4/LFXOUT | bidirectional | Low-frequency crystal oscillator output or general-purpose digital I/O pin with standard drive capability. |
| 9 | PA5/HFXIN | bidirectional | High-frequency crystal oscillator input or general-purpose digital I/O pin with standard drive capability. |
| 10 | PA6/HFXOUT | bidirectional | High-frequency crystal oscillator output or general-purpose digital I/O pin with standard drive capability. |
| 11 | PA7 | bidirectional | General-purpose digital I/O pin configurable as clock output, timer, or PWM with standard drive capability. |
| 12 | PA8 | bidirectional | General-purpose digital I/O pin configurable for UART, SPI, or timer functions with standard drive capability. |
| 13 | PA9 | bidirectional | High-speed general-purpose digital I/O pin configurable for UART, SPI, timer, or RTC output with high-speed I/O capability. |
| 14 | PA10 | bidirectional | High-drive general-purpose digital I/O pin configurable for UART, SPI, or timer functions with 20mA drive capability, supports wake from shutdown mode. |
| 15 | PA11 | bidirectional | High-drive general-purpose digital I/O pin configurable for UART, SPI, or timer functions with 20mA drive capability, supports wake from shutdown mode. |
| 16 | PA12 | bidirectional | High-speed general-purpose digital I/O pin configurable as UART3, SPI0, timer input, CAN transmit, or ADC channel A0_12. |
| 17 | PA13 | bidirectional | High-speed general-purpose digital I/O pin configurable as UART3, SPI0, timer, or CAN receive with high-speed I/O capability. |
| 18 | PA14 | bidirectional | High-speed ADC channel A0_12 or general-purpose digital I/O pin configurable for UART, SPI, timer, or clock output. |
| 19 | PA15 | bidirectional | ADC1 analog input channel A1_0 or general-purpose digital I/O pin with standard drive capability. |
| 20 | PA16 | bidirectional | ADC1 analog input channel A1_1 or general-purpose digital I/O pin configurable for SPI or timer functions. |
| 21 | PA17 | bidirectional | ADC1 analog input channel A1_2 or general-purpose digital I/O pin with wake capability from shutdown mode. |
| 22 | PA18 | bidirectional | ADC1 analog input channel A1_3 or GPAMP negative input or general-purpose digital I/O pin with wake capability from shutdown mode. |
| 23 | PA19/SWDIO | bidirectional | Serial wire debug data I/O pin (primary function) or general-purpose digital I/O with high-speed capability. |
| 24 | PA20/SWCLK | input | Serial wire debug clock input (primary function) or general-purpose digital I/O with standard drive capability. |
| 25 | PA21/VREF- | bidirectional | ADC1 analog input channel A1_7 or external voltage reference negative input/internal reference ground with standard drive capability. |
| 26 | PA22/GPAMP_OUT | bidirectional | ADC0 analog input channel A0_7 or general-purpose amplifier output or general-purpose digital I/O with standard drive capability. |
| 27 | PA23/VREF+ | bidirectional | External voltage reference positive input or internal reference output or general-purpose digital I/O for UART, SPI, or timer functions. |
| 28 | PA24 | bidirectional | ADC0 analog input channel A0_3 or general-purpose digital I/O pin configurable for UART, SPI, or timer functions. |
| 29 | PA25 | bidirectional | ADC0 analog input channel A0_2 or general-purpose digital I/O pin with standard drive capability. |
| 30 | PA26/GPAMP_IN+ | bidirectional | ADC0 analog input channel A0_1 or general-purpose amplifier positive input or general-purpose digital I/O with standard drive capability. |
| 31 | PA27 | bidirectional | ADC0 analog input channel A0_0 or general-purpose digital I/O pin configurable for RTC output or SPI/timer functions. |
| 32 | VCORE | power_out | Regulated core voltage output from on-chip LDO, requires 470nF bypass capacitor to VSS. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSPM0G3106SRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
mspm0g3106srhbr-etched.step/mspm0g3106srhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mspm0g3106srhbr.step/mspm0g3106srhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (69 pp, sha256
7c5df909316e74bc, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MSPM0G3106SRHBR
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-32(5x5)
MSPM0G3106SRHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA0 | bidirectional | General-purpose digital I/O pin configurable as UART0_TX, I2C0_SDA, TIMA0_C0, timer output, or FCC input with 5V tolerant open-drain capability. |
| 2 | PA1 | bidirectional | General-purpose digital I/O pin configurable as UART0_RX, I2C0_SCL, TIMA0_C1, timer input/output, or FCC input with 5V tolerant open-drain capability. |
| 3 | NRST | input | Reset input signal, active low; must be pulled high to VDD for device operation. |
| 4 | VDD | power_in | Main power supply voltage input, 1.62V to 3.6V recommended operating range. |
| 5 | VSS | power_in | Ground/reference voltage for power supply. |
| 6 | PA2/ROSC | bidirectional | General-purpose digital I/O or external precision resistor input for SYSOSC frequency correction loop when FCL is enabled. |
| 7 | PA3/LFXIN | bidirectional | Low-frequency crystal oscillator input or general-purpose digital I/O pin with standard drive capability. |
| 8 | PA4/LFXOUT | bidirectional | Low-frequency crystal oscillator output or general-purpose digital I/O pin with standard drive capability. |
| 9 | PA5/HFXIN | bidirectional | High-frequency crystal oscillator input or general-purpose digital I/O pin with standard drive capability. |
| 10 | PA6/HFXOUT | bidirectional | High-frequency crystal oscillator output or general-purpose digital I/O pin with standard drive capability. |
| 11 | PA7 | bidirectional | General-purpose digital I/O pin configurable as clock output, timer, or PWM with standard drive capability. |
| 12 | PA8 | bidirectional | General-purpose digital I/O pin configurable for UART, SPI, or timer functions with standard drive capability. |
| 13 | PA9 | bidirectional | High-speed general-purpose digital I/O pin configurable for UART, SPI, timer, or RTC output with high-speed I/O capability. |
| 14 | PA10 | bidirectional | High-drive general-purpose digital I/O pin configurable for UART, SPI, or timer functions with 20mA drive capability, supports wake from shutdown mode. |
| 15 | PA11 | bidirectional | High-drive general-purpose digital I/O pin configurable for UART, SPI, or timer functions with 20mA drive capability, supports wake from shutdown mode. |
| 16 | PA12 | bidirectional | High-speed general-purpose digital I/O pin configurable as UART3, SPI0, timer input, CAN transmit, or ADC channel A0_12. |
| 17 | PA13 | bidirectional | High-speed general-purpose digital I/O pin configurable as UART3, SPI0, timer, or CAN receive with high-speed I/O capability. |
| 18 | PA14 | bidirectional | High-speed ADC channel A0_12 or general-purpose digital I/O pin configurable for UART, SPI, timer, or clock output. |
| 19 | PA15 | bidirectional | ADC1 analog input channel A1_0 or general-purpose digital I/O pin with standard drive capability. |
| 20 | PA16 | bidirectional | ADC1 analog input channel A1_1 or general-purpose digital I/O pin configurable for SPI or timer functions. |
| 21 | PA17 | bidirectional | ADC1 analog input channel A1_2 or general-purpose digital I/O pin with wake capability from shutdown mode. |
| 22 | PA18 | bidirectional | ADC1 analog input channel A1_3 or GPAMP negative input or general-purpose digital I/O pin with wake capability from shutdown mode. |
| 23 | PA19/SWDIO | bidirectional | Serial wire debug data I/O pin (primary function) or general-purpose digital I/O with high-speed capability. |
| 24 | PA20/SWCLK | input | Serial wire debug clock input (primary function) or general-purpose digital I/O with standard drive capability. |
| 25 | PA21/VREF- | bidirectional | ADC1 analog input channel A1_7 or external voltage reference negative input/internal reference ground with standard drive capability. |
| 26 | PA22/GPAMP_OUT | bidirectional | ADC0 analog input channel A0_7 or general-purpose amplifier output or general-purpose digital I/O with standard drive capability. |
| 27 | PA23/VREF+ | bidirectional | External voltage reference positive input or internal reference output or general-purpose digital I/O for UART, SPI, or timer functions. |
| 28 | PA24 | bidirectional | ADC0 analog input channel A0_3 or general-purpose digital I/O pin configurable for UART, SPI, or timer functions. |
| 29 | PA25 | bidirectional | ADC0 analog input channel A0_2 or general-purpose digital I/O pin with standard drive capability. |
| 30 | PA26/GPAMP_IN+ | bidirectional | ADC0 analog input channel A0_1 or general-purpose amplifier positive input or general-purpose digital I/O with standard drive capability. |
| 31 | PA27 | bidirectional | ADC0 analog input channel A0_0 or general-purpose digital I/O pin configurable for RTC output or SPI/timer functions. |
| 32 | VCORE | power_out | Regulated core voltage output from on-chip LDO, requires 470nF bypass capacitor to VSS. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
## CAD (KiCad official)
- Symbol: `MSPM0G3106SRHBR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `mspm0g3106srhbr-etched.step` / `mspm0g3106srhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mspm0g3106srhbr.step` / `mspm0g3106srhbr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590920951809204224) (69 pp, sha256 `7c5df909316e74bc`, retrieved 2026-10-07, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mspm0g3106srhbr-datasheet.pdf)