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MSPM0G1106TRGZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0G1106TRGZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48(7x7)

MSPM0G1106TRGZR from Texas Instruments, in a VQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5 V tolerant open-drain I/O (ODIO) with alternate functions including UART0_TX, I2C0_SDA and FCC_IN; output-high needs an external pull-up because ODIO has no PMOS driver.
2 PA1 bidirectional 5 V tolerant open-drain I/O (ODIO) with alternate functions including UART0_RX and I2C0_SCL; output-high needs an external pull-up because ODIO has no PMOS driver.
3 PA28 bidirectional High-drive I/O (HDIO) that can wake the device from SHUTDOWN; the datasheet gives an absolute maximum HDIO pin current of 20 mA.
4 NRST input Active-low reset input that must be pulled up to VDD, otherwise the device cannot start; the datasheet suggests a 47 kΩ pull-up with 10 nF to ground.
5 PA31 bidirectional High-drive I/O (HDIO) that can wake the device from SHUTDOWN; alternate function includes CLK_OUT and UART0_RX.
6 VDD power_in Power supply, 1.62 V to 3.6 V recommended operating range (absolute maximum -0.3 V to 4.1 V); decouple with 10 µF and 0.1 µF low-ESR capacitors placed within a few millimetres of the pin.
7 VSS power_in Ground reference for the device.
8 PA2/ROSC bidirectional Standard digital I/O; when the SYSOSC frequency correction loop is used, this pin connects to a 100 kΩ ±0.1% ±25 ppm ROSC resistor to VSS, and if the FCL is not used it can be a GPIO.
9 PA3 bidirectional Standard digital I/O; also the LFXT 32.768 kHz crystal oscillator input.
10 PA4 bidirectional Standard digital I/O; also the LFXT 32.768 kHz crystal oscillator output and LFCLK_IN digital clock input alternate.
11 PA5 bidirectional Standard digital I/O; also the HFXT crystal oscillator input, which supports 4 MHz to 48 MHz crystals.
12 PA6 bidirectional Standard digital I/O; also the HFXT crystal oscillator output and HFCLK_IN digital clock input alternate (HFCLK_IN accepts 4 MHz to 48 MHz logic-level clocks).
13 PA7 bidirectional Standard digital I/O; configurable clock output (CLK_OUT) and timer alternate functions.
14 PB2 bidirectional Standard digital I/O; alternate functions include UART3_TX, UART2_CTS and I2C1_SCL.
15 PB3 bidirectional Standard digital I/O; alternate functions include UART3_RX, UART2_RTS and I2C1_SDA.
16 PA8 bidirectional Standard digital I/O; alternate functions include UART1_TX and SPI0_CS0.
17 PA9 bidirectional High-speed I/O (HSIO); alternate functions include RTC_OUT, CLK_OUT, UART1_RX and SPI0_PICO. HSIO output frequency is up to 16 MHz to 40 MHz depending on VDD and DRV setting.
18 PA10 bidirectional High-drive I/O (HDIO); alternate functions include UART0_TX, SPI0_POCI and I2C0_SDA.
19 PA11 bidirectional High-drive I/O (HDIO) that can wake the device from SHUTDOWN; alternate functions include UART0_RX, SPI0_SCK and I2C0_SCL.
20 PB6 bidirectional Standard digital I/O; alternate functions include UART1_TX and SPI1_CS0.
21 PB7 bidirectional Standard digital I/O; alternate functions include UART1_RX and SPI1_POCI.
22 PB8 bidirectional Standard digital I/O; alternate functions include UART1_CTS and SPI1_PICO.
23 PB9 bidirectional Standard digital I/O; alternate functions include UART1_RTS and SPI1_SCK.
24 PB14 bidirectional Standard digital I/O; alternate functions include SPI1_CS3 and SPI1_POCI.
25 PB15 bidirectional Standard digital I/O; alternate functions include UART2_TX and SPI1_PICO.
26 PB16 bidirectional Standard digital I/O; alternate functions include UART2_RX and SPI1_SCK.
27 PA12 bidirectional High-speed I/O (HSIO); alternate functions include UART3_CTS, SPI0_SCK and FCC_IN.
28 PA13 bidirectional High-speed I/O (HSIO); alternate functions include UART3_RTS, SPI0_POCI and UART3_RX.
29 PA14 bidirectional High-speed I/O (HSIO); also ADC0 analog input channel 12 (A0_12) and CLK_OUT.
30 PA15 bidirectional Standard digital I/O; also ADC1 analog input channel 0 (A1_0).
31 PA16 bidirectional Standard digital I/O; also ADC1 analog input channel 1 (A1_1) and FCC_IN.
32 PA17 bidirectional Standard digital I/O with wake-up from SHUTDOWN; also ADC1 analog input channel 2 (A1_2).
33 PA18 bidirectional Standard digital I/O with wake-up from SHUTDOWN; also ADC1 analog input 3 (A1_3) and the GPAMP inverting input (GPAMP_IN-).
34 PA19 bidirectional High-speed I/O (HSIO) used as the bidirectional serial wire debug data pin (SWDIO).
35 PA20 input Standard digital I/O used as the serial wire debug clock input (SWCLK) from the debug probe.
36 PB17 bidirectional Standard digital I/O; also ADC1 analog input channel 4 (A1_4).
37 PB18 bidirectional Standard digital I/O; also ADC1 analog input channel 5 (A1_5).
38 PB19 bidirectional Standard digital I/O; also ADC1 analog input channel 6 (A1_6).
39 PA21 bidirectional Standard digital I/O; also ADC1 analog input channel 7 (A1_7) and the VREF- ground-side reference pin for an external or internal voltage reference.
40 PA22 bidirectional Standard digital I/O; also ADC0 analog input channel 7 (A0_7) and the GPAMP output.
41 PB20 bidirectional Standard digital I/O; also ADC0 analog input channel 6 (A0_6).
42 PB24 bidirectional Standard digital I/O; also ADC0 analog input channel 5 (A0_5).
43 PA23 bidirectional Standard digital I/O; also the VREF+ voltage reference pin, used as an external reference input or internal reference output, which requires a decoupling capacitor between VREF+ and VREF-/GND.
44 PA24 bidirectional Standard digital I/O; also ADC0 analog input channel 3 (A0_3).
45 PA25 bidirectional Standard digital I/O; also ADC0 analog input channel 2 (A0_2).
46 PA26 bidirectional Standard digital I/O; also ADC0 analog input channel 1 (A0_1) and the GPAMP non-inverting input (GPAMP_IN+).
47 PA27 bidirectional Standard digital I/O; also ADC0 analog input channel 0 (A0_0) and RTC_OUT.
48 VCORE power_out Regulated core power output that requires a 0.47 µF (470 nF) capacitor placed close to the device; no external voltage or load may be applied to this pin.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: MSPM0G1106TRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: mspm0g1106trgzr-etched.step / mspm0g1106trgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g1106trgzr.step / mspm0g1106trgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (91 pp, sha256 2cddc09fb7f556fb, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF