component
MSP430I2020TRHBR
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MSP430I2020TRHBR
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)
MSP430I2020TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0.0+ | input | Positive analog input of SD24 channel A0.0; unused analog input pairs should be shorted and connected to analog ground. |
| 2 | A0.0- | input | Negative analog input of SD24 channel A0.0; unused analog input pairs should be shorted and connected to analog ground. |
| 3 | A1.0+ | input | Positive analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground. |
| 4 | A1.0- | input | Negative analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground. |
| 5 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 6 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 7 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 8 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 9 | VREF | power_in | External reference voltage input for SD24; with internal reference (SD24REFS = 1) the pin must not be loaded externally and only the recommended CVREF capacitor to AVSS is connected. |
| 10 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 11 | ROSC | passive | External resistor pin for the DCO; connect the recommended resistor to AVSS in external resistor mode or connect to AVSS in internal resistor mode, with no external DC loading or voltage applied. |
| 12 | DVSS | power_in | Digital supply voltage, negative terminal; TI recommends connecting the thermal pad to DVSS. |
| 13 | VCC | power_in | Analog and digital supply voltage, positive terminal; operating supply range is 2.2 V to 3.6 V. |
| 14 | VCORE | power_out | Regulated core power supply for internal use only; no external DC loading or voltage is allowed, and only the recommended CVCORE (470 nF) capacitor is connected. |
| 15 | RST/NMI/SBWTDIO | bidirectional | Reset or nonmaskable interrupt input, and Spy-Bi-Wire test data input/output for device programming and test. |
| 16 | TEST/SBWTCK | input | Selects test mode for the JTAG pins on P1.0 to P1.3, and serves as the Spy-Bi-Wire test clock input; the pin always has an internal pulldown enabled. |
| 17 | P1.0/UCA0STE/MCLK/TCK | bidirectional | General-purpose digital I/O with eUSCI_A0 SPI slave transmit enable, MCLK output, and JTAG test clock input (TCK). |
| 18 | P1.1/UCA0CLK/SMCLK/TMS | bidirectional | General-purpose digital I/O with eUSCI_A0 clock input/output, SMCLK output, and JTAG test mode select input (TMS). |
| 19 | P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK | bidirectional | General-purpose digital I/O with eUSCI_A0 UART receive or SPI slave out/master in, ACLK output, and JTAG test data or test clock input. |
| 20 | P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI | bidirectional | General-purpose digital I/O with eUSCI_A0 UART transmit or SPI slave in/master out, Timer TA0 external clock input TACLK, and JTAG test data output (TDO/TDI). |
| 21 | P1.4/UCB0STE/TA0.0 | bidirectional | General-purpose digital I/O with eUSCI_B0 SPI slave transmit enable and Timer TA0 CCR0 capture input (CCI0A) or compare output (Out0). |
| 22 | P1.5/UCB0CLK/TA0.1 | bidirectional | General-purpose digital I/O with eUSCI_B0 clock input/output and Timer TA0 CCR1 capture input (CCI1A) or compare output (Out1). |
| 23 | P1.6/UCB0SCL/UCB0SOMI/TA0.2 | bidirectional | General-purpose digital I/O with eUSCI_B0 I2C clock or SPI slave out/master in, and Timer TA0 CCR2 capture input (CCI2A) or compare output (Out2). |
| 24 | P1.7/UCB0SDA/UCB0SIMO/TA1CLK | bidirectional | General-purpose digital I/O with eUSCI_B0 I2C data or SPI slave in/master out, and Timer TA1 external clock input TACLK. |
| 25 | P2.0/TA1.0/CLKIN | bidirectional | General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0A) or compare output (Out0), and DCO bypass clock input (CLKIN). |
| 26 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O with Timer TA1 CCR1 capture input (CCI1A) or compare output (Out1). |
| 27 | P2.2/TA1.2 | bidirectional | General-purpose digital I/O with Timer TA1 CCR2 capture input (CCI2A) or compare output (Out2). |
| 28 | P2.3/VMONIN | bidirectional | General-purpose digital I/O that doubles as the voltage monitor input (VMONIN) when VMONLVLx is set to 3'b111 in the VMONCTL register. |
| 29 | P2.4/TA1.0 | bidirectional | General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package. |
| 30 | P2.5/TA0.0 | bidirectional | General-purpose digital I/O with Timer TA0 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package. |
| 31 | P2.6/TA0.1 | bidirectional | General-purpose digital I/O with Timer TA0 CCR1 compare output (Out1); available only on the 32-pin RHB package. |
| 32 | P2.7/TA0.2 | bidirectional | General-purpose digital I/O with Timer TA0 CCR2 compare output (Out2); available only on the 32-pin RHB package. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430I2020TRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
msp430i2020trhbr-etched.step/msp430i2020trhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430i2020trhbr.step/msp430i2020trhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (81 pp, sha256
491d1dfb5ddef2e2, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MSP430I2020TRHBR
**Texas Instruments** · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)
MSP430I2020TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0.0+ | input | Positive analog input of SD24 channel A0.0; unused analog input pairs should be shorted and connected to analog ground. |
| 2 | A0.0- | input | Negative analog input of SD24 channel A0.0; unused analog input pairs should be shorted and connected to analog ground. |
| 3 | A1.0+ | input | Positive analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground. |
| 4 | A1.0- | input | Negative analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground. |
| 5 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 6 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 7 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 8 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |
| 9 | VREF | power_in | External reference voltage input for SD24; with internal reference (SD24REFS = 1) the pin must not be loaded externally and only the recommended CVREF capacitor to AVSS is connected. |
| 10 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 11 | ROSC | passive | External resistor pin for the DCO; connect the recommended resistor to AVSS in external resistor mode or connect to AVSS in internal resistor mode, with no external DC loading or voltage applied. |
| 12 | DVSS | power_in | Digital supply voltage, negative terminal; TI recommends connecting the thermal pad to DVSS. |
| 13 | VCC | power_in | Analog and digital supply voltage, positive terminal; operating supply range is 2.2 V to 3.6 V. |
| 14 | VCORE | power_out | Regulated core power supply for internal use only; no external DC loading or voltage is allowed, and only the recommended CVCORE (470 nF) capacitor is connected. |
| 15 | RST/NMI/SBWTDIO | bidirectional | Reset or nonmaskable interrupt input, and Spy-Bi-Wire test data input/output for device programming and test. |
| 16 | TEST/SBWTCK | input | Selects test mode for the JTAG pins on P1.0 to P1.3, and serves as the Spy-Bi-Wire test clock input; the pin always has an internal pulldown enabled. |
| 17 | P1.0/UCA0STE/MCLK/TCK | bidirectional | General-purpose digital I/O with eUSCI_A0 SPI slave transmit enable, MCLK output, and JTAG test clock input (TCK). |
| 18 | P1.1/UCA0CLK/SMCLK/TMS | bidirectional | General-purpose digital I/O with eUSCI_A0 clock input/output, SMCLK output, and JTAG test mode select input (TMS). |
| 19 | P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK | bidirectional | General-purpose digital I/O with eUSCI_A0 UART receive or SPI slave out/master in, ACLK output, and JTAG test data or test clock input. |
| 20 | P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI | bidirectional | General-purpose digital I/O with eUSCI_A0 UART transmit or SPI slave in/master out, Timer TA0 external clock input TACLK, and JTAG test data output (TDO/TDI). |
| 21 | P1.4/UCB0STE/TA0.0 | bidirectional | General-purpose digital I/O with eUSCI_B0 SPI slave transmit enable and Timer TA0 CCR0 capture input (CCI0A) or compare output (Out0). |
| 22 | P1.5/UCB0CLK/TA0.1 | bidirectional | General-purpose digital I/O with eUSCI_B0 clock input/output and Timer TA0 CCR1 capture input (CCI1A) or compare output (Out1). |
| 23 | P1.6/UCB0SCL/UCB0SOMI/TA0.2 | bidirectional | General-purpose digital I/O with eUSCI_B0 I2C clock or SPI slave out/master in, and Timer TA0 CCR2 capture input (CCI2A) or compare output (Out2). |
| 24 | P1.7/UCB0SDA/UCB0SIMO/TA1CLK | bidirectional | General-purpose digital I/O with eUSCI_B0 I2C data or SPI slave in/master out, and Timer TA1 external clock input TACLK. |
| 25 | P2.0/TA1.0/CLKIN | bidirectional | General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0A) or compare output (Out0), and DCO bypass clock input (CLKIN). |
| 26 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O with Timer TA1 CCR1 capture input (CCI1A) or compare output (Out1). |
| 27 | P2.2/TA1.2 | bidirectional | General-purpose digital I/O with Timer TA1 CCR2 capture input (CCI2A) or compare output (Out2). |
| 28 | P2.3/VMONIN | bidirectional | General-purpose digital I/O that doubles as the voltage monitor input (VMONIN) when VMONLVLx is set to 3'b111 in the VMONCTL register. |
| 29 | P2.4/TA1.0 | bidirectional | General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package. |
| 30 | P2.5/TA0.0 | bidirectional | General-purpose digital I/O with Timer TA0 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package. |
| 31 | P2.6/TA0.1 | bidirectional | General-purpose digital I/O with Timer TA0 CCR1 compare output (Out1); available only on the 32-pin RHB package. |
| 32 | P2.7/TA0.2 | bidirectional | General-purpose digital I/O with Timer TA0 CCR2 compare output (Out2); available only on the 32-pin RHB package. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 33 |
## CAD (KiCad official)
- Symbol: `MSP430I2020TRHBR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `msp430i2020trhbr-etched.step` / `msp430i2020trhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430i2020trhbr.step` / `msp430i2020trhbr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430i2031) (81 pp, sha256 `491d1dfb5ddef2e2`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/msp430i2020trhbr-datasheet.pdf)