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MSP430I2020TRHBR
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Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# MSP430I2020TRHBR++**Texas Instruments** · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)++MSP430I2020TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A0.0+ | input | Positive analog input of SD24 channel A0.0; unused analog input pairs should be shorted and connected to analog ground. |+| 2 | A0.0- | input | Negative analog input of SD24 channel A0.0; unused analog input pairs should be shorted and connected to analog ground. |+| 3 | A1.0+ | input | Positive analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground. |+| 4 | A1.0- | input | Negative analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground. |+| 5 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |+| 6 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |+| 7 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |+| 8 | NC | unconnected | Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS. |+| 9 | VREF | power_in | External reference voltage input for SD24; with internal reference (SD24REFS = 1) the pin must not be loaded externally and only the recommended CVREF capacitor to AVSS is connected. |+| 10 | AVSS | power_in | Analog supply voltage, negative terminal. |+| 11 | ROSC | passive | External resistor pin for the DCO; connect the recommended resistor to AVSS in external resistor mode or connect to AVSS in internal resistor mode, with no external DC loading or voltage applied. |+| 12 | DVSS | power_in | Digital supply voltage, negative terminal; TI recommends connecting the thermal pad to DVSS. |+| 13 | VCC | power_in | Analog and digital supply voltage, positive terminal; operating supply range is 2.2 V to 3.6 V. |+| 14 | VCORE | power_out | Regulated core power supply for internal use only; no external DC loading or voltage is allowed, and only the recommended CVCORE (470 nF) capacitor is connected. |+| 15 | RST/NMI/SBWTDIO | bidirectional | Reset or nonmaskable interrupt input, and Spy-Bi-Wire test data input/output for device programming and test. |+| 16 | TEST/SBWTCK | input | Selects test mode for the JTAG pins on P1.0 to P1.3, and serves as the Spy-Bi-Wire test clock input; the pin always has an internal pulldown enabled. |+| 17 | P1.0/UCA0STE/MCLK/TCK | bidirectional | General-purpose digital I/O with eUSCI_A0 SPI slave transmit enable, MCLK output, and JTAG test clock input (TCK). |+| 18 | P1.1/UCA0CLK/SMCLK/TMS | bidirectional | General-purpose digital I/O with eUSCI_A0 clock input/output, SMCLK output, and JTAG test mode select input (TMS). |+| 19 | P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK | bidirectional | General-purpose digital I/O with eUSCI_A0 UART receive or SPI slave out/master in, ACLK output, and JTAG test data or test clock input. |+| 20 | P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI | bidirectional | General-purpose digital I/O with eUSCI_A0 UART transmit or SPI slave in/master out, Timer TA0 external clock input TACLK, and JTAG test data output (TDO/TDI). |+| 21 | P1.4/UCB0STE/TA0.0 | bidirectional | General-purpose digital I/O with eUSCI_B0 SPI slave transmit enable and Timer TA0 CCR0 capture input (CCI0A) or compare output (Out0). |+| 22 | P1.5/UCB0CLK/TA0.1 | bidirectional | General-purpose digital I/O with eUSCI_B0 clock input/output and Timer TA0 CCR1 capture input (CCI1A) or compare output (Out1). |+| 23 | P1.6/UCB0SCL/UCB0SOMI/TA0.2 | bidirectional | General-purpose digital I/O with eUSCI_B0 I2C clock or SPI slave out/master in, and Timer TA0 CCR2 capture input (CCI2A) or compare output (Out2). |+| 24 | P1.7/UCB0SDA/UCB0SIMO/TA1CLK | bidirectional | General-purpose digital I/O with eUSCI_B0 I2C data or SPI slave in/master out, and Timer TA1 external clock input TACLK. |+| 25 | P2.0/TA1.0/CLKIN | bidirectional | General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0A) or compare output (Out0), and DCO bypass clock input (CLKIN). |+| 26 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O with Timer TA1 CCR1 capture input (CCI1A) or compare output (Out1). |+| 27 | P2.2/TA1.2 | bidirectional | General-purpose digital I/O with Timer TA1 CCR2 capture input (CCI2A) or compare output (Out2). |+| 28 | P2.3/VMONIN | bidirectional | General-purpose digital I/O that doubles as the voltage monitor input (VMONIN) when VMONLVLx is set to 3'b111 in the VMONCTL register. |+| 29 | P2.4/TA1.0 | bidirectional | General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package. |+| 30 | P2.5/TA0.0 | bidirectional | General-purpose digital I/O with Timer TA0 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package. |+| 31 | P2.6/TA0.1 | bidirectional | General-purpose digital I/O with Timer TA0 CCR1 compare output (Out1); available only on the 32-pin RHB package. |+| 32 | P2.7/TA0.2 | bidirectional | General-purpose digital I/O with Timer TA0 CCR2 compare output (Out2); available only on the 32-pin RHB package. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | Single Chip Microcomputer/Microcontroller |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `MSP430I2020TRHBR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `msp430i2020trhbr-etched.step` / `msp430i2020trhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430i2020trhbr.step` / `msp430i2020trhbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430i2031) (81 pp, sha256 `491d1dfb5ddef2e2`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430i2020trhbr-datasheet.pdf)
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unused analog input pairs should be shorted and connected to analog ground."+ },+ {+ "number": "2",+ "name": "A0.0-",+ "type": "input",+ "description": "Negative analog input of SD24 channel A0.0; unused analog input pairs should be shorted and connected to analog ground."+ },+ {+ "number": "3",+ "name": "A1.0+",+ "type": "input",+ "description": "Positive analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground."+ },+ {+ "number": "4",+ "name": "A1.0-",+ "type": "input",+ "description": "Negative analog input of SD24 channel A1.0; unused analog input pairs should be shorted and connected to analog ground."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS."+ },+ {+ "number": "8",+ "name": "NC",+ "type": "unconnected",+ "description": "Not connected on the MSP430i2021/i2020 RHB package; TI recommends connecting NC pins to AVSS."+ },+ {+ "number": "9",+ "name": "VREF",+ "type": "power_in",+ "description": "External reference voltage input for SD24; with internal reference (SD24REFS = 1) the pin must not be loaded externally and only the recommended CVREF capacitor to AVSS is connected."+ },+ {+ "number": "10",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog supply voltage, negative terminal."+ },+ {+ "number": "11",+ "name": "ROSC",+ "type": "passive",+ "description": "External resistor pin for the DCO; connect the recommended resistor to AVSS in external resistor mode or connect to AVSS in internal resistor mode, with no external DC loading or voltage applied."+ },+ {+ "number": "12",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital supply voltage, negative terminal; TI recommends connecting the thermal pad to DVSS."+ },+ {+ "number": "13",+ "name": "VCC",+ "type": "power_in",+ "description": "Analog and digital supply voltage, positive terminal; operating supply range is 2.2 V to 3.6 V."+ },+ {+ "number": "14",+ "name": "VCORE",+ "type": "power_out",+ "description": "Regulated core power supply for internal use only; no external DC loading or voltage is allowed, and only the recommended CVCORE (470 nF) capacitor is connected."+ },+ {+ "number": "15",+ "name": "RST/NMI/SBWTDIO",+ "type": "bidirectional",+ "description": "Reset or nonmaskable interrupt input, and Spy-Bi-Wire test data input/output for device programming and test."+ },+ {+ "number": "16",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Selects test mode for the JTAG pins on P1.0 to P1.3, and serves as the Spy-Bi-Wire test clock input; the pin always has an internal pulldown enabled."+ },+ {+ "number": "17",+ "name": "P1.0/UCA0STE/MCLK/TCK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_A0 SPI slave transmit enable, MCLK output, and JTAG test clock input (TCK)."+ },+ {+ "number": "18",+ "name": "P1.1/UCA0CLK/SMCLK/TMS",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_A0 clock input/output, SMCLK output, and JTAG test mode select input (TMS)."+ },+ {+ "number": "19",+ "name": "P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_A0 UART receive or SPI slave out/master in, ACLK output, and JTAG test data or test clock input."+ },+ {+ "number": "20",+ "name": "P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_A0 UART transmit or SPI slave in/master out, Timer TA0 external clock input TACLK, and JTAG test data output (TDO/TDI)."+ },+ {+ "number": "21",+ "name": "P1.4/UCB0STE/TA0.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_B0 SPI slave transmit enable and Timer TA0 CCR0 capture input (CCI0A) or compare output (Out0)."+ },+ {+ "number": "22",+ "name": "P1.5/UCB0CLK/TA0.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_B0 clock input/output and Timer TA0 CCR1 capture input (CCI1A) or compare output (Out1)."+ },+ {+ "number": "23",+ "name": "P1.6/UCB0SCL/UCB0SOMI/TA0.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_B0 I2C clock or SPI slave out/master in, and Timer TA0 CCR2 capture input (CCI2A) or compare output (Out2)."+ },+ {+ "number": "24",+ "name": "P1.7/UCB0SDA/UCB0SIMO/TA1CLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with eUSCI_B0 I2C data or SPI slave in/master out, and Timer TA1 external clock input TACLK."+ },+ {+ "number": "25",+ "name": "P2.0/TA1.0/CLKIN",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0A) or compare output (Out0), and DCO bypass clock input (CLKIN)."+ },+ {+ "number": "26",+ "name": "P2.1/TA1.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer TA1 CCR1 capture input (CCI1A) or compare output (Out1)."+ },+ {+ "number": "27",+ "name": "P2.2/TA1.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer TA1 CCR2 capture input (CCI2A) or compare output (Out2)."+ },+ {+ "number": "28",+ "name": "P2.3/VMONIN",+ "type": "bidirectional",+ "description": "General-purpose digital I/O that doubles as the voltage monitor input (VMONIN) when VMONLVLx is set to 3'b111 in the VMONCTL register."+ },+ {+ "number": "29",+ "name": "P2.4/TA1.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer TA1 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package."+ },+ {+ "number": "30",+ "name": "P2.5/TA0.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer TA0 CCR0 capture input (CCI0B) or compare output (Out0); available only on the 32-pin RHB package."+ },+ {+ "number": "31",+ "name": "P2.6/TA0.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer TA0 CCR1 compare output (Out1); available only on the 32-pin RHB package."+ },+ {+ "number": "32",+ "name": "P2.7/TA0.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer TA0 CCR2 compare output (Out2); available only on the 32-pin RHB package."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The VQFN package has an exposed thermal pad. It is not numbered in the datasheet pin diagram, so it ; Pin 9 is labelled VREF in the pin diagram and signal table, so VREF is listed with type input. The d; The pin diagram for MSP430i2021/MSP430i2020 RHB shows NC at pins 5 to 8. The MSP430I2020 falls under",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 32,+ "cost_usd": 0.1911,+ "at": "2026-10-08T15:03:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430i2031",+ "pages": 81,+ "sha256": "491d1dfb5ddef2e2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430i2020trhbr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430i2020trhbr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "a210c973680995621ceee972ebc543d9a3bf5a775ef393093dfa58f5c7bcf752",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}