component
MSP430G2402IPW20R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownMSP430G2402IPW20R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
MSP430G2402IPW20R from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Positive digital supply voltage, rated 1.8 V to 3.6 V for normal operation |
| 2 | P1.0/TA0CLK/ACLK/A0 | bidirectional | Port 1 I/O bit 0; selectable as Timer0_A clock input (TA0CLK), ACLK signal output, or ADC10 analog input A0 (MSP430G2x32 only) |
| 3 | P1.1/TA0.0/A1 | bidirectional | Port 1 I/O bit 1; selectable as Timer0_A capture/compare output (TA0.0) or ADC10 analog input A1 (MSP430G2x32 only) |
| 4 | P1.2/TA0.1/A2 | bidirectional | Port 1 I/O bit 2; selectable as Timer0_A capture/compare output (TA0.1) or ADC10 analog input A2 (MSP430G2x32 only) |
| 5 | P1.3/ADC10CLK/A3/VREF-/VEREF- | bidirectional | Port 1 I/O bit 3; selectable as ADC10 conversion clock output, ADC10 analog input A3, or negative reference voltage (MSP430G2x32 only) |
| 6 | P1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK | bidirectional | Port 1 I/O bit 4; selectable as Timer0_A capture/compare output (TA0.2), SMCLK signal output, ADC10 analog input A4 (MSP430G2x32 only), positive reference voltage (MSP430G2x32 only), or JTAG test clock input |
| 7 | P1.5/TA0.0/A5/SCLK/TMS | bidirectional | Port 1 I/O bit 5; selectable as Timer0_A output (TA0.0), ADC10 analog input A5 (MSP430G2x32 only), USI serial clock, or JTAG test mode select |
| 8 | P2.0 | bidirectional | Port 2 I/O bit 0 with edge-selectable interrupt capability and programmable pull-down resistor |
| 9 | P2.1 | bidirectional | Port 2 I/O bit 1 with edge-selectable interrupt capability and programmable pull-down resistor |
| 10 | P2.2 | bidirectional | Port 2 I/O bit 2 with edge-selectable interrupt capability and programmable pull-down resistor |
| 11 | P2.3 | bidirectional | Port 2 I/O bit 3 with edge-selectable interrupt capability and programmable pull-down resistor |
| 12 | P2.4 | bidirectional | Port 2 I/O bit 4 with edge-selectable interrupt capability and programmable pull-down resistor |
| 13 | P2.5 | bidirectional | Port 2 I/O bit 5 with edge-selectable interrupt capability and programmable pull-down resistor |
| 14 | P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK | bidirectional | Port 1 I/O bit 6; selectable as Timer0_A compare output (TA0.1), ADC10 analog input A6 (MSP430G2x32 only), USI serial data output (SDO), USI I2C clock (SCL), or JTAG test data input (TDI) |
| 15 | P1.7/SDI/SDA/A7/TDO/TDI | bidirectional | Port 1 I/O bit 7; selectable as USI serial data input (SDI), USI I2C data line (SDA), ADC10 analog input A7 (MSP430G2x32 only), or JTAG test data output/input (TDO/TDI) |
| 16 | RST/NMI/SBWTDIO | input | External reset input or nonmaskable interrupt input; also serves as Spy-Bi-Wire test data I/O during device programming; pulse width t(reset) must be ≥2 µs |
| 17 | TEST/SBWTCK | input | Test mode selection input for JTAG interface pins on Port 1; also serves as Spy-Bi-Wire test clock input; device protection fuse is connected to this pin |
| 18 | XOUT/P2.7 | bidirectional | Crystal oscillator output terminal or Port 2 I/O bit 7; oscillator driver remains connected until P2SEL.7 is cleared; excess current flows if used as input |
| 19 | XIN/P2.6/TA0.1 | bidirectional | Crystal oscillator input terminal or Port 2 I/O bit 6; selectable as Timer0_A compare output (TA0.1) when configured as P2.6 |
| 20 | DVSS | power_in | Digital ground reference |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
MSP430G2402IPW20R - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
msp430g2402ipw20r-etched.step/msp430g2402ipw20r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430g2402ipw20r.step/msp430g2402ipw20r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (77 pp, sha256
6df2cd5fcd8d8260, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).