component
MSP430FR6870IPMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MSP430FR6870IPMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430FR6870IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3/UCA0SOMI/UCA0RXD/UCB1STE/S4 | bidirectional | General-purpose I/O P4.3 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A0 SOMI/RXD, eUSCI_B1 STE and LCD segment S4. |
| 2 | P1.4/UCB0CLK/UCA0STE/TA1.0/S3 | bidirectional | General-purpose I/O P1.4 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B0 CLK, eUSCI_A0 STE, Timer_A1 TA1.0 and LCD segment S3. |
| 3 | P1.5/UCB0STE/UCA0CLK/TA0.0/S2 | bidirectional | General-purpose I/O P1.5 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B0 STE, eUSCI_A0 CLK, Timer_A0 TA0.0 and LCD segment S2. |
| 4 | P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1 | bidirectional | General-purpose I/O P1.6 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B0 SIMO/SDA, Timer_A0 TA0.1, BSL_DAT (I2C BSL devices) and LCD segment S1. |
| 5 | P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0 | bidirectional | General-purpose I/O P1.7 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B0 SOMI/SCL, Timer_A0 TA0.2, BSL_CLK (I2C BSL devices) and LCD segment S0. |
| 6 | R33/LCDCAP | bidirectional | Most positive analog LCD voltage (V1) I/O and LCD capacitor connection; if not used it can be tied to DVSS or DVCC. |
| 7 | P6.0/R23 | bidirectional | General-purpose I/O P6.0 (reset default, LVCMOS powered from DVCC) that also serves as the second most positive analog LCD voltage (V2) I/O. |
| 8 | P6.1/R13/LCDREF | bidirectional | General-purpose I/O P6.1 (reset default, LVCMOS powered from DVCC) that also serves as the third most positive LCD voltage (V3 or V4) I/O and external LCD reference voltage input LCDREF. |
| 9 | P6.2/COUT/R03 | bidirectional | General-purpose I/O P6.2 (reset default, LVCMOS powered from DVCC) shared with comparator output COUT and the lowest analog LCD voltage (V5) I/O R03. |
| 10 | P6.3/COM0 | bidirectional | General-purpose I/O P6.3 (reset default, LVCMOS powered from DVCC) shared with LCD common output COM0. |
| 11 | P6.4/TB0.0/COM1/S30 | bidirectional | General-purpose I/O P6.4 (reset default, LVCMOS powered from DVCC) shared with Timer_B0 TB0.0, LCD common output COM1 and LCD segment S30. |
| 12 | P6.5/TB0.1/COM2/S29 | bidirectional | General-purpose I/O P6.5 (reset default, LVCMOS powered from DVCC) shared with Timer_B0 TB0.1, LCD common output COM2 and LCD segment S29. |
| 13 | P6.6/TB0.2/COM3/S28 | bidirectional | General-purpose I/O P6.6 (reset default, LVCMOS powered from DVCC) shared with Timer_B0 TB0.2, LCD common output COM3 and LCD segment S28. |
| 14 | P3.0/UCB1CLK/TA3.2/S27 | bidirectional | General-purpose I/O P3.0 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B1 CLK, Timer_A3 TA3.2 and LCD segment S27. |
| 15 | P3.1/UCB1SIMO/UCB1SDA/TA3.3/S26 | bidirectional | General-purpose I/O P3.1 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B1 SIMO/SDA, Timer_A3 TA3.3 and LCD segment S26. |
| 16 | P3.2/UCB1SOMI/UCB1SCL/TA3.4/S25 | bidirectional | General-purpose I/O P3.2 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B1 SOMI/SCL, Timer_A3 TA3.4 and LCD segment S25. |
| 17 | DVSS1 | power_in | Digital ground supply; all DVSS and AVSS pins are to be held at VSS = 0 V. |
| 18 | DVCC1 | power_in | Digital power supply; VCC of 1.8 V to 3.6 V must be applied at all DVCC and AVCC pins. |
| 19 | TEST/SBWTCK | input | Test mode pin used to select digital I/O on the JTAG pins, which has an internal pulldown enabled, and Spy-Bi-Wire input clock SBWTCK. |
| 20 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input RST (or nonmaskable interrupt input NMI when configured) with Spy-Bi-Wire data I/O SBWTDIO; external reset pulse must be at least 2 µs. |
| 21 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 | bidirectional | General-purpose I/O PJ.0 (reset default) that is the JTAG test data output TDO, with TB0OUTH input, SMCLK output and low-power debug signal SRSCG1. |
| 22 | PJ.1/TDI/TCLK/MCLK/SRSCG0 | bidirectional | General-purpose I/O PJ.1 (reset default) that is the JTAG test data input TDI/TCLK, with MCLK output and low-power debug signal SRSCG0. |
| 23 | PJ.2/TMS/ACLK/SROSCOFF | bidirectional | General-purpose I/O PJ.2 (reset default) that is the JTAG test mode select TMS, with ACLK output and low-power debug signal SROSCOFF. |
| 24 | PJ.3/TCK/COUT/SRCPUOFF | bidirectional | General-purpose I/O PJ.3 (reset default) that is the JTAG test clock TCK, with comparator output COUT and low-power debug signal SRCPUOFF. |
| 25 | P3.3/TA1.1/TB0CLK/S24 | bidirectional | General-purpose I/O P3.3 (reset default, LVCMOS powered from DVCC) shared with Timer_A1 TA1.1, Timer_B0 clock input TB0CLK and LCD segment S24. |
| 26 | P3.4/UCA1SIMO/UCA1TXD/TB0.0/S23 | bidirectional | General-purpose I/O P3.4 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A1 SIMO/TXD, Timer_B0 TB0.0 and LCD segment S23. |
| 27 | P3.5/UCA1SOMI/UCA1RXD/TB0.1/S22 | bidirectional | General-purpose I/O P3.5 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A1 SOMI/RXD, Timer_B0 TB0.1 and LCD segment S22. |
| 28 | P3.6/UCA1CLK/TB0.2/S21 | bidirectional | General-purpose I/O P3.6 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A1 CLK, Timer_B0 TB0.2 and LCD segment S21. |
| 29 | P3.7/UCA1STE/TB0.3/S20 | bidirectional | General-purpose I/O P3.7 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A1 STE, Timer_B0 TB0.3 and LCD segment S20. |
| 30 | P2.3/UCA0STE/TB0OUTH/S19 | bidirectional | General-purpose I/O P2.3 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A0 STE, TB0OUTH (switches all Timer_B PWM outputs high impedance) and LCD segment S19. |
| 31 | P2.2/UCA0CLK/TB0.4/RTCCLK/S18 | bidirectional | General-purpose I/O P2.2 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A0 CLK, Timer_B0 TB0.4, RTC clock output RTCCLK and LCD segment S18. |
| 32 | P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S17 | bidirectional | General-purpose I/O P2.1 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A0 SOMI/RXD, BSL_RX (UART BSL devices), Timer_B0 TB0.5, DMA external trigger DMAE0 and LCD segment S17. |
| 33 | P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S16 | bidirectional | General-purpose I/O P2.0 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A0 SIMO/TXD, BSL_TX (UART BSL devices), Timer_B0 TB0.6, TB0CLK and LCD segment S16. |
| 34 | P7.0/TA0CLK/S15 | bidirectional | General-purpose I/O P7.0 (reset default, LVCMOS powered from DVCC) shared with Timer_A0 clock input TA0CLK and LCD segment S15. |
| 35 | P7.1/TA0.0/ACLK/S14 | bidirectional | General-purpose I/O P7.1 (reset default, LVCMOS powered from DVCC) shared with Timer_A0 TA0.0, ACLK output and LCD segment S14. |
| 36 | P7.2/TA0.1/S13 | bidirectional | General-purpose I/O P7.2 (reset default, LVCMOS powered from DVCC) shared with Timer_A0 TA0.1 and LCD segment S13. |
| 37 | P7.3/TA0.2/S12 | bidirectional | General-purpose I/O P7.3 (reset default, LVCMOS powered from DVCC) shared with Timer_A0 TA0.2 and LCD segment S12. |
| 38 | P7.4/SMCLK/S11 | bidirectional | General-purpose I/O P7.4 (reset default, LVCMOS powered from DVCC) shared with SMCLK output and LCD segment S11. |
| 39 | DVSS2 | power_in | Digital ground supply; held at VSS = 0 V. |
| 40 | DVCC2 | power_in | Digital power supply; VCC of 1.8 V to 3.6 V must be applied at all DVCC and AVCC pins. |
| 41 | P1.3/TA1.2/A3/C3 | bidirectional | General-purpose I/O P1.3 (reset default) shared with Timer_A1 TA1.2 and ADC analog input A3 and comparator input C3. |
| 42 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose I/O P1.2 (reset default) shared with Timer_A1 TA1.1, Timer_A0 clock TA0CLK, comparator output COUT, ADC input A2 and comparator input C2. |
| 43 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose I/O P1.1 (reset default) shared with Timer_A0 TA0.2, Timer_A1 clock TA1CLK, comparator output COUT, ADC input A1, comparator input C1, positive reference output VREF+ and external positive reference input VeREF+. |
| 44 | P1.0/TA0.1/RTCCLK/DMAE0/A0/C0/VREF-/VeREF- | bidirectional | General-purpose I/O P1.0 (reset default) shared with Timer_A0 TA0.1, RTC clock output RTCCLK, DMA trigger DMAE0, ADC input A0, comparator input C0, negative reference output VREF- and external negative reference input VeREF-. |
| 45 | P9.4/A12/C12 | bidirectional | General-purpose I/O P9.4 (reset default) shared with ADC analog input A12 and comparator input C12. |
| 46 | P9.5/A13/C13 | bidirectional | General-purpose I/O P9.5 (reset default) shared with ADC analog input A13 and comparator input C13. |
| 47 | P9.6/A14/C14 | bidirectional | General-purpose I/O P9.6 (reset default) shared with ADC analog input A14 and comparator input C14. |
| 48 | P9.7/A15/C15 | bidirectional | General-purpose I/O P9.7 (reset default) shared with ADC analog input A15 and comparator input C15. |
| 49 | AVCC1 | power_in | Analog power supply; VCC of 1.8 V to 3.6 V must be applied at all AVCC pins, with DVCC-to-AVCC difference within ±0.3 V. |
| 50 | AVSS1 | power_in | Analog ground supply; held at VSS = 0 V. |
| 51 | PJ.4/LFXIN | input | Port PJ.4 (reset default) that is the input of the 32-kHz crystal oscillator LFXT (or bypass clock input when LFXTBYPASS is set). |
| 52 | PJ.5/LFXOUT | output | Port PJ.5 (reset default) that is the output terminal of the 32-kHz crystal oscillator LFXT; if used as digital I/O it is connected through a 4-pF capacitor and 35-MΩ resistor in series. |
| 53 | AVSS2 | power_in | Analog ground supply; held at VSS = 0 V. |
| 54 | PJ.7/HFXOUT | output | Port PJ.7 (reset default) that is the output terminal of the high-frequency crystal oscillator HFXT on the MSP430FR687x package. |
| 55 | PJ.6/HFXIN | input | Port PJ.6 (reset default) that is the input terminal of the high-frequency crystal oscillator HFXT (or bypass clock input when HFXTBYPASS is set). |
| 56 | AVSS3 | power_in | Analog ground supply; held at VSS = 0 V. |
| 57 | P5.7/UCA1STE/TB0CLK/S10 | bidirectional | General-purpose I/O P5.7 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A1 STE, Timer_B0 clock TB0CLK and LCD segment S10. |
| 58 | P4.4/UCB1STE/TA1CLK/S9 | bidirectional | General-purpose I/O P4.4 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B1 STE, Timer_A1 clock TA1CLK and LCD segment S9. |
| 59 | P4.5/UCB1CLK/TA1.0/S8 | bidirectional | General-purpose I/O P4.5 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B1 CLK, Timer_A1 TA1.0 and LCD segment S8. |
| 60 | P4.6/UCB1SIMO/UCB1SDA/TA1.1/S7 | bidirectional | General-purpose I/O P4.6 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B1 SIMO/SDA, Timer_A1 TA1.1 and LCD segment S7. |
| 61 | P4.7/UCB1SOMI/UCB1SCL/TA1.2/S6 | bidirectional | General-purpose I/O P4.7 (reset default, LVCMOS powered from DVCC) shared with eUSCI_B1 SOMI/SCL, Timer_A1 TA1.2 and LCD segment S6. |
| 62 | DVSS3 | power_in | Digital ground supply; held at VSS = 0 V. |
| 63 | DVCC3 | power_in | Digital power supply; VCC of 1.8 V to 3.6 V must be applied at all DVCC and AVCC pins. |
| 64 | P4.2/UCA0SIMO/UCA0TXD/UCB1CLK/S5 | bidirectional | General-purpose I/O P4.2 (reset default, LVCMOS powered from DVCC) shared with eUSCI_A0 SIMO/TXD, eUSCI_B1 CLK and LCD segment S5. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
MSP430FR6870IPMR - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
msp430fr6870ipmr-etched.step/msp430fr6870ipmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr6870ipmr.step/msp430fr6870ipmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (164 pp, sha256
acfa8c28f070a26c, retrieved 2026-10-12, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).