MSP430FR2633IRHBT

{
  "slug": "msp430fr2633irhbt",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "msp430fr2633irhbt",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "msp430fr2633irhbt.kicad_sym",
    "msp430fr2633irhbt.kicad_mod",
    "msp430fr2633irhbt.glb",
    "msp430fr2633irhbt.step",
    "msp430fr2633irhbt.lbr",
    "docs/hero.png",
    "docs/msp430fr2633irhbt-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "msp430fr2633irhbt-hero.glb",
    "msp430fr2633irhbt-hero.overlay.json"
  ],
  "component": {
    "mpn": "MSP430FR2633IRHBT",
    "manufacturer": "Texas Instruments",
    "package": "QFN-32-EP(5x5)",
    "pin_count": 33,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/msp430fr2633",
    "parts": {
      "symbol": "msp430fr2633irhbt.kicad_sym",
      "footprint": "msp430fr2633irhbt.kicad_mod",
      "model_3d": "msp430fr2633irhbt-hero.glb",
      "model_3d_plain": "msp430fr2633irhbt.glb",
      "model_3d_step": "msp430fr2633irhbt-etched.step",
      "model_3d_step_plain": "msp430fr2633irhbt.step",
      "lbr": "msp430fr2633irhbt.lbr"
    },
    "distributor_links": {
      "lcsc": "C173299",
      "digikey": "296-43405-2-ND",
      "mouser": "595-MSP430FR2633RHBT"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T18:22:57Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-43405-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-MSP430FR2633RHBT",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "RST/NMI/SBWTDIO",
        "type": "bidirectional",
        "description": "Reset input (RST, reset default) with NMI and Spy-Bi-Wire data I/O (SBWTDIO); if unused, terminate with a 47 kΩ pullup or the internal pullup with a 10 nF (or 1.1 nF) pulldown."
      },
      {
        "number": "2",
        "name": "TEST/SBWTCK",
        "type": "input",
        "description": "TEST is the test mode pin (selected digital I/O on JTAG pins) with an internal pulldown that is always enabled, and SBWTCK is the Spy-Bi-Wire input clock; leave TEST open if unused."
      },
      {
        "number": "3",
        "name": "P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 TXD/SIMO, Timer_A1 CCR2, JTAG TCK, ADC input A4 and VREF+ output selectable by function control."
      },
      {
        "number": "4",
        "name": "P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 RXD/SOMI, Timer_A1 CCR1, JTAG TMS and ADC input A5 selectable by function control."
      },
      {
        "number": "5",
        "name": "P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 CLK, Timer_A1 clock input, JTAG TDI/TCLK and ADC input A6 selectable by function control."
      },
      {
        "number": "6",
        "name": "P1.7/UCA0STE/SMCLK/TDO/A7",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 STE, SMCLK output, JTAG TDO and ADC input A7 selectable by function control."
      },
      {
        "number": "7",
        "name": "P1.0/UCB0STE/TA0CLK/A0/Veref+",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 STE, Timer_A0 clock input, ADC input A0, and ADC positive reference Veref+ input."
      },
      {
        "number": "8",
        "name": "P1.1/UCB0CLK/TA0.1/A1",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 CLK, Timer_A0 CCR1 and ADC input A1 selectable by function control."
      },
      {
        "number": "9",
        "name": "P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 SIMO/SDA, Timer_A0 CCR2, ADC input A2 and ADC negative reference Veref- input."
      },
      {
        "number": "10",
        "name": "P1.3/UCB0SOMI/UCB0SCL/MCLK/A3",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 SOMI/SCL, MCLK output and ADC input A3 selectable by function control."
      },
      {
        "number": "11",
        "name": "P2.2/SYNC/ACLK",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with CapTIvate synchronous trigger input SYNC and ACLK output (ACLK maximum 40 kHz per the recommended operating conditions)."
      },
      {
        "number": "12",
        "name": "P3.0/CAP0.0",
        "type": "bidirectional",
        "description": "General-purpose I/O (DVCC, reset state OFF) that can alternatively be a CapTIvate channel CAP0.0 analog I/O powered from VREG."
      },
      {
        "number": "13",
        "name": "CAP0.1",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP0.1 analog I/O powered from VREG (reset state OFF); leave open if unused, as CAPx.1 pins have internal pullup and pulldown resistors with high impedance as default."
      },
      {
        "number": "14",
        "name": "P2.3/CAP0.2",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) that can alternatively be CapTIvate channel CAP0.2 analog I/O powered from VREG."
      },
      {
        "number": "15",
        "name": "CAP0.3",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP0.3 analog I/O powered from VREG (reset state OFF); leave open if unused."
      },
      {
        "number": "16",
        "name": "P3.1/UCA1STE/CAP1.0",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 STE, or alternatively CapTIvate channel CAP1.0 analog I/O powered from VREG."
      },
      {
        "number": "17",
        "name": "P2.4/UCA1CLK/CAP1.1",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 CLK, or alternatively CapTIvate channel CAP1.1 analog I/O powered from VREG."
      },
      {
        "number": "18",
        "name": "P2.5/UCA1RXD/UCA1SOMI/CAP1.2",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 RXD/SOMI, or alternatively CapTIvate channel CAP1.2 analog I/O powered from VREG."
      },
      {
        "number": "19",
        "name": "P2.6/UCA1TXD/UCA1SIMO/CAP1.3",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 TXD/SIMO, or alternatively CapTIvate channel CAP1.3 analog I/O powered from VREG; leave open if unused."
      },
      {
        "number": "20",
        "name": "VREG",
        "type": "power_out",
        "description": "Decoupling pin for the CapTIvate regulator, which requires a recommended 1 µF capacitor with ESR ≤ 200 mΩ."
      },
      {
        "number": "21",
        "name": "CAP2.0",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP2.0 analog I/O powered from VREG (reset state OFF); leave open if unused."
      },
      {
        "number": "22",
        "name": "CAP2.1",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP2.1 analog I/O powered from VREG (reset state OFF); leave open if unused."
      },
      {
        "number": "23",
        "name": "CAP2.2",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP2.2 analog I/O powered from VREG (reset state OFF); leave open if unused."
      },
      {
        "number": "24",
        "name": "CAP2.3",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP2.3 analog I/O powered from VREG (reset state OFF); leave open if unused."
      },
      {
        "number": "25",
        "name": "P2.7/CAP3.0",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset state OFF) that can alternatively be CapTIvate channel CAP3.0 analog I/O powered from VREG."
      },
      {
        "number": "26",
        "name": "CAP3.1",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP3.1 analog I/O powered from VREG (reset state OFF); leave open if unused."
      },
      {
        "number": "27",
        "name": "P3.2/CAP3.2",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP3.2 analog I/O (the port-P3.2 function is shown in the pin diagram), with the CapTIvate function powered from 1.5 V VREG while GPIO is powered from 3.3 V DVCC."
      },
      {
        "number": "28",
        "name": "CAP3.3",
        "type": "bidirectional",
        "description": "CapTIvate channel CAP3.3 analog I/O powered from VREG; leave open if unused."
      },
      {
        "number": "29",
        "name": "P2.0/XOUT",
        "type": "output",
        "description": "Output terminal for the 32 kHz crystal oscillator (XOUT); when XT1BYPASS mode is used with a digital clock on XIN, this pin can be used for other purposes."
      },
      {
        "number": "30",
        "name": "P2.1/XIN",
        "type": "input",
        "description": "Input terminal for the low-frequency 32 kHz crystal oscillator (XIN); the device supports only a 32 kHz crystal here, or a digital clock when XT1BYPASS mode is selected."
      },
      {
        "number": "31",
        "name": "DVSS",
        "type": "power_in",
        "description": "Digital supply ground for the MCU; inferred by elimination as the only remaining power pin, see review_required."
      },
      {
        "number": "32",
        "name": "DVCC",
        "type": "power_in",
        "description": "Main digital and analog supply input; the recommended operating supply is 1.8 V to 3.6 V with a 4.7 µF to 10 µF bypass capacitor, inferred by elimination, see review_required."
      },
      {
        "number": "33",
        "name": "VQFN Pad",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers for CAP3.2, CAP3.3, XOUT and XIN come from Table 4-2 (page 17). The Table 4-1 rows for R; The supplied text never explicitly assigns DVSS and DVCC to pin numbers 31 and 32 for the RHB packag; The VQFN exposed thermal pad (Table 4-2) is not a numbered pin in the text. It is excluded from the ",
          "exposed pad 33 added from the footprint"
        ],
        "pages_sent": 46,
        "cost_usd": 0.2578,
        "at": "2026-10-08T18:22:20"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/msp430fr2633",
        "pages": 111,
        "sha256": "99ff2112334bfba1",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 33,
        "described": 33,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "msp430fr2633irhbt.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          5.0,
          5.0,
          0.875
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "msp430fr2633irhbt-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          5.0,
          5.0,
          0.875
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "071e3f98b95ce9bc30d5af5f93f26ea23bd01ebae35a146fa4845fac0a9736f7",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}