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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

MSP430FR2633IRHBT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)

MSP430FR2633IRHBT from Texas Instruments, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RST/NMI/SBWTDIO	bidirectional	Reset input (RST, reset default) with NMI and Spy-Bi-Wire data I/O (SBWTDIO); if unused, terminate with a 47 kΩ pullup or the internal pullup with a 10 nF (or 1.1 nF) pulldown.
2	TEST/SBWTCK	input	TEST is the test mode pin (selected digital I/O on JTAG pins) with an internal pulldown that is always enabled, and SBWTCK is the Spy-Bi-Wire input clock; leave TEST open if unused.
3	P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 TXD/SIMO, Timer_A1 CCR2, JTAG TCK, ADC input A4 and VREF+ output selectable by function control.
4	P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 RXD/SOMI, Timer_A1 CCR1, JTAG TMS and ADC input A5 selectable by function control.
5	P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 CLK, Timer_A1 clock input, JTAG TDI/TCLK and ADC input A6 selectable by function control.
6	P1.7/UCA0STE/SMCLK/TDO/A7	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A0 STE, SMCLK output, JTAG TDO and ADC input A7 selectable by function control.
7	P1.0/UCB0STE/TA0CLK/A0/Veref+	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 STE, Timer_A0 clock input, ADC input A0, and ADC positive reference Veref+ input.
8	P1.1/UCB0CLK/TA0.1/A1	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 CLK, Timer_A0 CCR1 and ADC input A1 selectable by function control.
9	P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 SIMO/SDA, Timer_A0 CCR2, ADC input A2 and ADC negative reference Veref- input.
10	P1.3/UCB0SOMI/UCB0SCL/MCLK/A3	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_B0 SOMI/SCL, MCLK output and ADC input A3 selectable by function control.
11	P2.2/SYNC/ACLK	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with CapTIvate synchronous trigger input SYNC and ACLK output (ACLK maximum 40 kHz per the recommended operating conditions).
12	P3.0/CAP0.0	bidirectional	General-purpose I/O (DVCC, reset state OFF) that can alternatively be a CapTIvate channel CAP0.0 analog I/O powered from VREG.
13	CAP0.1	bidirectional	CapTIvate channel CAP0.1 analog I/O powered from VREG (reset state OFF); leave open if unused, as CAPx.1 pins have internal pullup and pulldown resistors with high impedance as default.
14	P2.3/CAP0.2	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) that can alternatively be CapTIvate channel CAP0.2 analog I/O powered from VREG.
15	CAP0.3	bidirectional	CapTIvate channel CAP0.3 analog I/O powered from VREG (reset state OFF); leave open if unused.
16	P3.1/UCA1STE/CAP1.0	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 STE, or alternatively CapTIvate channel CAP1.0 analog I/O powered from VREG.
17	P2.4/UCA1CLK/CAP1.1	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 CLK, or alternatively CapTIvate channel CAP1.1 analog I/O powered from VREG.
18	P2.5/UCA1RXD/UCA1SOMI/CAP1.2	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 RXD/SOMI, or alternatively CapTIvate channel CAP1.2 analog I/O powered from VREG.
19	P2.6/UCA1TXD/UCA1SIMO/CAP1.3	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) with eUSCI_A1 TXD/SIMO, or alternatively CapTIvate channel CAP1.3 analog I/O powered from VREG; leave open if unused.
20	VREG	power_out	Decoupling pin for the CapTIvate regulator, which requires a recommended 1 µF capacitor with ESR ≤ 200 mΩ.
21	CAP2.0	bidirectional	CapTIvate channel CAP2.0 analog I/O powered from VREG (reset state OFF); leave open if unused.
22	CAP2.1	bidirectional	CapTIvate channel CAP2.1 analog I/O powered from VREG (reset state OFF); leave open if unused.
23	CAP2.2	bidirectional	CapTIvate channel CAP2.2 analog I/O powered from VREG (reset state OFF); leave open if unused.
24	CAP2.3	bidirectional	CapTIvate channel CAP2.3 analog I/O powered from VREG (reset state OFF); leave open if unused.
25	P2.7/CAP3.0	bidirectional	General-purpose LVCMOS I/O powered from DVCC (reset state OFF) that can alternatively be CapTIvate channel CAP3.0 analog I/O powered from VREG.
26	CAP3.1	bidirectional	CapTIvate channel CAP3.1 analog I/O powered from VREG (reset state OFF); leave open if unused.
27	P3.2/CAP3.2	bidirectional	CapTIvate channel CAP3.2 analog I/O (the port-P3.2 function is shown in the pin diagram), with the CapTIvate function powered from 1.5 V VREG while GPIO is powered from 3.3 V DVCC.
28	CAP3.3	bidirectional	CapTIvate channel CAP3.3 analog I/O powered from VREG; leave open if unused.
29	P2.0/XOUT	output	Output terminal for the 32 kHz crystal oscillator (XOUT); when XT1BYPASS mode is used with a digital clock on XIN, this pin can be used for other purposes.
30	P2.1/XIN	input	Input terminal for the low-frequency 32 kHz crystal oscillator (XIN); the device supports only a 32 kHz crystal here, or a digital clock when XT1BYPASS mode is selected.
31	DVSS	power_in	Digital supply ground for the MCU; inferred by elimination as the only remaining power pin, see review_required.
32	DVCC	power_in	Main digital and analog supply input; the recommended operating supply is 1.8 V to 3.6 V with a 4.7 µF to 10 µF bypass capacitor, inferred by elimination, see review_required.
33	VQFN Pad	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-32-EP(5x5)
Category	Embedded Processors & Controllers
Pins	33

CAD (KiCad official)

Symbol: MSP430FR2633IRHBT
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: msp430fr2633irhbt-etched.step / msp430fr2633irhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr2633irhbt.step / msp430fr2633irhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (111 pp, sha256 99ff2112334bfba1, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF