# MSP430FR2522IPW16R

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · TSSOP-16

MSP430FR2522IPW16R from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1 | bidirectional | General-purpose I/O P1.1, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0CLK, ACLK, A1/VREF+ analog input and CAP1.1 CapTIvate channel (CAP1.x available only on MSP430FR2522). |
| 2 | P1.0 | bidirectional | General-purpose I/O P1.0, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0STE, A0/Veref+ analog input and CAP1.0 CapTIvate channel (MSP430FR2522 only). |
| 3 | TEST | input | Test mode pin used with JTAG/Spy-Bi-Wire; it always has an internal pull-down enabled, so it can be left open when unused. Also serves as SBWTCK clock input. |
| 4 | RST/NMI/SBWTDIO | input | Active-low reset input (RST) or NMI input, also the SBWTDIO Spy-Bi-Wire data I/O; when unused, use a 47-kΩ pullup or internal pullup with a 10-nF (or 1.1-nF) pulldown. |
| 5 | DVCC | power_in | Supply voltage input for the digital and analog modules, 1.8 V to 3.6 V at the DVCC pin; decouple with 4.7 µF to 10 µF plus 0.1 µF placed close to the pin. |
| 6 | DVSS | power_in | Ground reference for DVCC; all voltages are referenced to VSS, and separated grounds with a single-point connection are recommended. |
| 7 | P2.1 | bidirectional | General-purpose I/O P2.1, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0RXD, UCA0SOMI and XIN input for the 32-kHz crystal oscillator. |
| 8 | P2.0 | bidirectional | General-purpose I/O P2.0, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0TXD, UCA0SIMO and XOUT output for the 32-kHz crystal oscillator. |
| 9 | P2.2 | bidirectional | General-purpose I/O P2.2, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also TA1.1, SYNC CapTIvate synchronous trigger input and A4 analog input. |
| 10 | P1.7 | bidirectional | General-purpose I/O P1.7, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0STE, TDO JTAG test data output and CAP0.3 CapTIvate channel. |
| 11 | P1.6 | bidirectional | General-purpose I/O P1.6, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0CLK, TA0CLK, JTAG TDI/TCLK test data/clock input and CAP0.2 CapTIvate channel. |
| 12 | P1.5 | bidirectional | General-purpose I/O P1.5, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0RXD, UCA0SOMI, TA0.2, JTAG TMS mode select and CAP0.1 CapTIvate channel. |
| 13 | P1.4 | bidirectional | General-purpose I/O P1.4, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0TXD, UCA0SIMO, TA0.1, JTAG TCK test clock and CAP0.0 CapTIvate channel. |
| 14 | VREG | power_out | Decoupling pin for the CapTIvate internal regulator; a 1-µF capacitor with ESR ≤ 200 mΩ is recommended. |
| 15 | P1.3 | bidirectional | General-purpose I/O P1.3, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0SOMI, UCB0SCL, MCLK output, A3 analog input and CAP1.3 CapTIvate channel (MSP430FR2522 only). |
| 16 | P1.2 | bidirectional | General-purpose I/O P1.2, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0SIMO, UCB0SDA, SMCLK output, A2 analog input, Veref- ADC negative reference and CAP1.2 CapTIvate channel (MSP430FR2522 only). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Embedded Processors & Controllers |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `MSP430FR2522IPW16R`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `msp430fr2522ipw16r-etched.step` / `msp430fr2522ipw16r-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr2522ipw16r.step` / `msp430fr2522ipw16r.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr2512) (94 pp, sha256 `bb8d4e10a575dcaf`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430fr2522ipw16r-datasheet.pdf)