component
MSP430FR2522IPW16R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+53@@ -0,0 +1,53 @@+# MSP430FR2522IPW16R++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · TSSOP-16++MSP430FR2522IPW16R from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P1.1 | bidirectional | General-purpose I/O P1.1, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0CLK, ACLK, A1/VREF+ analog input and CAP1.1 CapTIvate channel (CAP1.x available only on MSP430FR2522). |+| 2 | P1.0 | bidirectional | General-purpose I/O P1.0, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0STE, A0/Veref+ analog input and CAP1.0 CapTIvate channel (MSP430FR2522 only). |+| 3 | TEST | input | Test mode pin used with JTAG/Spy-Bi-Wire; it always has an internal pull-down enabled, so it can be left open when unused. Also serves as SBWTCK clock input. |+| 4 | RST/NMI/SBWTDIO | input | Active-low reset input (RST) or NMI input, also the SBWTDIO Spy-Bi-Wire data I/O; when unused, use a 47-kΩ pullup or internal pullup with a 10-nF (or 1.1-nF) pulldown. |+| 5 | DVCC | power_in | Supply voltage input for the digital and analog modules, 1.8 V to 3.6 V at the DVCC pin; decouple with 4.7 µF to 10 µF plus 0.1 µF placed close to the pin. |+| 6 | DVSS | power_in | Ground reference for DVCC; all voltages are referenced to VSS, and separated grounds with a single-point connection are recommended. |+| 7 | P2.1 | bidirectional | General-purpose I/O P2.1, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0RXD, UCA0SOMI and XIN input for the 32-kHz crystal oscillator. |+| 8 | P2.0 | bidirectional | General-purpose I/O P2.0, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0TXD, UCA0SIMO and XOUT output for the 32-kHz crystal oscillator. |+| 9 | P2.2 | bidirectional | General-purpose I/O P2.2, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also TA1.1, SYNC CapTIvate synchronous trigger input and A4 analog input. |+| 10 | P1.7 | bidirectional | General-purpose I/O P1.7, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0STE, TDO JTAG test data output and CAP0.3 CapTIvate channel. |+| 11 | P1.6 | bidirectional | General-purpose I/O P1.6, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0CLK, TA0CLK, JTAG TDI/TCLK test data/clock input and CAP0.2 CapTIvate channel. |+| 12 | P1.5 | bidirectional | General-purpose I/O P1.5, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0RXD, UCA0SOMI, TA0.2, JTAG TMS mode select and CAP0.1 CapTIvate channel. |+| 13 | P1.4 | bidirectional | General-purpose I/O P1.4, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0TXD, UCA0SIMO, TA0.1, JTAG TCK test clock and CAP0.0 CapTIvate channel. |+| 14 | VREG | power_out | Decoupling pin for the CapTIvate internal regulator; a 1-µF capacitor with ESR ≤ 200 mΩ is recommended. |+| 15 | P1.3 | bidirectional | General-purpose I/O P1.3, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0SOMI, UCB0SCL, MCLK output, A3 analog input and CAP1.3 CapTIvate channel (MSP430FR2522 only). |+| 16 | P1.2 | bidirectional | General-purpose I/O P1.2, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0SIMO, UCB0SDA, SMCLK output, A2 analog input, Veref- ADC negative reference and CAP1.2 CapTIvate channel (MSP430FR2522 only). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Embedded Processors & Controllers |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `MSP430FR2522IPW16R`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `msp430fr2522ipw16r-etched.step` / `msp430fr2522ipw16r-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr2522ipw16r.step` / `msp430fr2522ipw16r.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr2512) (94 pp, sha256 `bb8d4e10a575dcaf`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430fr2522ipw16r-datasheet.pdf)
page.jsonadded+247@@ -0,0 +1,247 @@+{+ "slug": "msp430fr2522ipw16r",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp430fr2522ipw16r",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp430fr2522ipw16r.kicad_sym",+ "msp430fr2522ipw16r.kicad_mod",+ "msp430fr2522ipw16r.glb",+ "msp430fr2522ipw16r.step",+ "msp430fr2522ipw16r.lbr",+ "docs/hero.png",+ "docs/msp430fr2522ipw16r-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp430fr2522ipw16r-hero.glb",+ "msp430fr2522ipw16r-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP430FR2522IPW16R",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp430fr2512",+ "parts": {+ "symbol": "msp430fr2522ipw16r.kicad_sym",+ "footprint": "msp430fr2522ipw16r.kicad_mod",+ "model_3d": "msp430fr2522ipw16r-hero.glb",+ "model_3d_plain": "msp430fr2522ipw16r.glb",+ "model_3d_step": "msp430fr2522ipw16r-etched.step",+ "model_3d_step_plain": "msp430fr2522ipw16r.step",+ "lbr": "msp430fr2522ipw16r.lbr"+ },+ "distributor_links": {+ "lcsc": "C191432",+ "digikey": "296-MSP430FR2522IPW16RTR-ND",+ "mouser": "595-430FR2522IPW16R"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:06:56Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-MSP430FR2522IPW16RTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-430FR2522IPW16R",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "P1.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.1, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0CLK, ACLK, A1/VREF+ analog input and CAP1.1 CapTIvate channel (CAP1.x available only on MSP430FR2522)."+ },+ {+ "number": "2",+ "name": "P1.0",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.0, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0STE, A0/Veref+ analog input and CAP1.0 CapTIvate channel (MSP430FR2522 only)."+ },+ {+ "number": "3",+ "name": "TEST",+ "type": "input",+ "description": "Test mode pin used with JTAG/Spy-Bi-Wire; it always has an internal pull-down enabled, so it can be left open when unused. Also serves as SBWTCK clock input."+ },+ {+ "number": "4",+ "name": "RST/NMI/SBWTDIO",+ "type": "input",+ "description": "Active-low reset input (RST) or NMI input, also the SBWTDIO Spy-Bi-Wire data I/O; when unused, use a 47-kΩ pullup or internal pullup with a 10-nF (or 1.1-nF) pulldown."+ },+ {+ "number": "5",+ "name": "DVCC",+ "type": "power_in",+ "description": "Supply voltage input for the digital and analog modules, 1.8 V to 3.6 V at the DVCC pin; decouple with 4.7 µF to 10 µF plus 0.1 µF placed close to the pin."+ },+ {+ "number": "6",+ "name": "DVSS",+ "type": "power_in",+ "description": "Ground reference for DVCC; all voltages are referenced to VSS, and separated grounds with a single-point connection are recommended."+ },+ {+ "number": "7",+ "name": "P2.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.1, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0RXD, UCA0SOMI and XIN input for the 32-kHz crystal oscillator."+ },+ {+ "number": "8",+ "name": "P2.0",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.0, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0TXD, UCA0SIMO and XOUT output for the 32-kHz crystal oscillator."+ },+ {+ "number": "9",+ "name": "P2.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.2, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also TA1.1, SYNC CapTIvate synchronous trigger input and A4 analog input."+ },+ {+ "number": "10",+ "name": "P1.7",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.7, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0STE, TDO JTAG test data output and CAP0.3 CapTIvate channel."+ },+ {+ "number": "11",+ "name": "P1.6",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.6, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0CLK, TA0CLK, JTAG TDI/TCLK test data/clock input and CAP0.2 CapTIvate channel."+ },+ {+ "number": "12",+ "name": "P1.5",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.5, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0RXD, UCA0SOMI, TA0.2, JTAG TMS mode select and CAP0.1 CapTIvate channel."+ },+ {+ "number": "13",+ "name": "P1.4",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.4, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCA0TXD, UCA0SIMO, TA0.1, JTAG TCK test clock and CAP0.0 CapTIvate channel."+ },+ {+ "number": "14",+ "name": "VREG",+ "type": "power_out",+ "description": "Decoupling pin for the CapTIvate internal regulator; a 1-µF capacitor with ESR ≤ 200 mΩ is recommended."+ },+ {+ "number": "15",+ "name": "P1.3",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.3, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0SOMI, UCB0SCL, MCLK output, A3 analog input and CAP1.3 CapTIvate channel (MSP430FR2522 only)."+ },+ {+ "number": "16",+ "name": "P1.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.2, high-impedance with Schmitt trigger and pullup/pulldown disabled after BOR; also UCB0SIMO, UCB0SDA, SMCLK output, A2 analog input, Veref- ADC negative reference and CAP1.2 CapTIvate channel (MSP430FR2522 only)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Figure 4-2 (16-pin PW top view) text layer is scrambled, so the pin-to-name mapping was taken from t; Pin 4 is listed as RST/NMI/SBWTDIO; the datasheet gives RST and NMI as input and SBWTDIO as I/O. Typ; Pin 14 VREG is a regulator output for CapTIvate decoupling, not a supply input; typed as power_out. "+ ],+ "pages_sent": 41,+ "cost_usd": 0.2017,+ "at": "2026-10-08T01:06:38"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430fr2512",+ "pages": 94,+ "sha256": "bb8d4e10a575dcaf",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430fr2522ipw16r.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430fr2522ipw16r-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "1224859e34f1414a3deaf9ee2c045edcdc6413d69a53e80c20fc42fefec8ac01",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}