MSP430FR2310IPW16R

{
  "slug": "msp430fr2310ipw16r",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "msp430fr2310ipw16r",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "msp430fr2310ipw16r.kicad_sym",
    "msp430fr2310ipw16r.kicad_mod",
    "msp430fr2310ipw16r.glb",
    "msp430fr2310ipw16r.step",
    "msp430fr2310ipw16r.lbr",
    "docs/hero.png",
    "docs/msp430fr2310ipw16r-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "msp430fr2310ipw16r-hero.glb",
    "msp430fr2310ipw16r-hero.overlay.json"
  ],
  "component": {
    "mpn": "MSP430FR2310IPW16R",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/msp430fr2311",
    "parts": {
      "symbol": "msp430fr2310ipw16r.kicad_sym",
      "footprint": "msp430fr2310ipw16r.kicad_mod",
      "model_3d": "msp430fr2310ipw16r-hero.glb",
      "model_3d_plain": "msp430fr2310ipw16r.glb",
      "model_3d_step": "msp430fr2310ipw16r-etched.step",
      "model_3d_step_plain": "msp430fr2310ipw16r.step",
      "lbr": "msp430fr2310ipw16r.lbr"
    },
    "distributor_links": {
      "lcsc": "C1339034",
      "digikey": "296-51444-2-ND",
      "mouser": "595-P430FR2310IPW16R"
    },
    "distributor_check": {
      "checked_at": "2026-10-11T03:22:28Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-51444-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-P430FR2310IPW16R",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "P1.1/UCB0CLK/ACLK/C1/A1",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 clock, ACLK output, eCOMP0 comparator input C1 and ADC input A1."
      },
      {
        "number": "2",
        "name": "P1.0/UCB0STE/SMCLK/C0/A0/Veref+",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 slave transmit enable, SMCLK output, eCOMP0 comparator input C0, ADC input A0 and ADC positive reference Veref+."
      },
      {
        "number": "3",
        "name": "TEST/SBWTCK",
        "type": "input",
        "description": "TEST is the Test Mode pin that selects digital I/O on the JTAG pins and always has an internal pulldown enabled, so it should be left open if unused; it also carries SBWTCK, the Spy-Bi-Wire input clock."
      },
      {
        "number": "4",
        "name": "RST/NMI/SBWTDIO",
        "type": "bidirectional",
        "description": "Active-low reset input (RST), also the nonmaskable interrupt input (NMI) and Spy-Bi-Wire data input/output (SBWTDIO); if unused, tie to DVCC with a 47-kΩ pullup or internal pullup and a 10-nF (or 1.1-nF with SBW) pulldown."
      },
      {
        "number": "5",
        "name": "DVCC",
        "type": "power_in",
        "description": "Main power supply for the digital and analog modules, specified at 1.8 V to 3.6 V, with a recommended 4.7 µF to 10 µF capacitor at DVCC."
      },
      {
        "number": "6",
        "name": "DVSS",
        "type": "power_in",
        "description": "Power ground for the digital and analog modules, at 0 V reference."
      },
      {
        "number": "7",
        "name": "P2.7/TB0CLK/XIN",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with Timer_B0 clock input TB0CLK and the crystal oscillator input XIN."
      },
      {
        "number": "8",
        "name": "P2.6/MCLK/XOUT",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with the MCLK output and the crystal oscillator output XOUT."
      },
      {
        "number": "9",
        "name": "P2.0/TB1.1/COUT",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with Timer_B1 capture/compare channel TB1.1 and the eCOMP0 comparator output COUT."
      },
      {
        "number": "10",
        "name": "P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 UART transmit or SPI SIMO, Timer_B0 channel TB0.2, JTAG TDO, TIA0 positive input TRI0+, ADC input A7, and VREF+ reference output (ground referenced)."
      },
      {
        "number": "11",
        "name": "P1.6 / UCA0RXD / UCA0SOMI / TB0.1 / TDI / TCLK / A6",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 UART receive or SPI SOMI, Timer_B0 channel TB0.1, JTAG TDI/TCLK and ADC input A6; TI recommends disabling the pin interrupt while in JTAG debug."
      },
      {
        "number": "12",
        "name": "TRI0-",
        "type": "input",
        "description": "Dedicated low-leakage TIA0 negative input pad that exists only in the TSSOP-16 package, with leakage reduced to 5 pA; leave open if unused (the pin is then a high-impedance output)."
      },
      {
        "number": "13",
        "name": "P1.5/UCA0CLK/TMS/TRI0O/A5",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 clock, JTAG TMS, TIA0 output TRI0O and ADC input A5."
      },
      {
        "number": "14",
        "name": "P1.4/UCA0STE/TCK/OA0+/A4",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 slave transmit enable, JTAG TCK, SAC0 op-amp positive input OA0+ and ADC input A4."
      },
      {
        "number": "15",
        "name": "P1.3/UCB0SOMI/UCB0SCL/OA0O/A3",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 SPI SOMI or I2C SCL, SAC0 op-amp output OA0O and ADC input A3."
      },
      {
        "number": "16",
        "name": "P1.2 / UCB0SIMO / UCB0SDA / TB0TRG / OA0- / A2 / Veref-",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 SPI SIMO or I2C SDA, Timer_B0 external trigger TB0TRG, SAC0 op-amp negative input OA0-, ADC input A2 and ADC negative reference Veref-."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin 12 is TRI0- and exists only on the TSSOP-16 package (Table 4-1 and Table 4-2, PW16 column). The ; Pin numbers were taken from the PW16 column of Table 4-1 and Table 4-2 because the pin-diagram text ; P2.1 through P2.5 are not bonded out on the 16-pin TSSOP, so they are omitted from this pinout. P2.0"
        ],
        "pages_sent": 39,
        "cost_usd": 0.2046,
        "at": "2026-10-11T03:22:12"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/msp430fr2311",
        "pages": 99,
        "sha256": "ace23ae4fc6ae702",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "msp430fr2310ipw16r.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "msp430fr2310ipw16r-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "add7074a619a472118eb75bdbba6d1b315c6ec9946cde51c37562abd5bbcfcaa",
        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}