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MSP430FR2310IPW16R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownMSP430FR2310IPW16R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-16
MSP430FR2310IPW16R from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1/UCB0CLK/ACLK/C1/A1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 clock, ACLK output, eCOMP0 comparator input C1 and ADC input A1. |
| 2 | P1.0/UCB0STE/SMCLK/C0/A0/Veref+ | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 slave transmit enable, SMCLK output, eCOMP0 comparator input C0, ADC input A0 and ADC positive reference Veref+. |
| 3 | TEST/SBWTCK | input | TEST is the Test Mode pin that selects digital I/O on the JTAG pins and always has an internal pulldown enabled, so it should be left open if unused; it also carries SBWTCK, the Spy-Bi-Wire input clock. |
| 4 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (RST), also the nonmaskable interrupt input (NMI) and Spy-Bi-Wire data input/output (SBWTDIO); if unused, tie to DVCC with a 47-kΩ pullup or internal pullup and a 10-nF (or 1.1-nF with SBW) pulldown. |
| 5 | DVCC | power_in | Main power supply for the digital and analog modules, specified at 1.8 V to 3.6 V, with a recommended 4.7 µF to 10 µF capacitor at DVCC. |
| 6 | DVSS | power_in | Power ground for the digital and analog modules, at 0 V reference. |
| 7 | P2.7/TB0CLK/XIN | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with Timer_B0 clock input TB0CLK and the crystal oscillator input XIN. |
| 8 | P2.6/MCLK/XOUT | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with the MCLK output and the crystal oscillator output XOUT. |
| 9 | P2.0/TB1.1/COUT | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with Timer_B1 capture/compare channel TB1.1 and the eCOMP0 comparator output COUT. |
| 10 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+ | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 UART transmit or SPI SIMO, Timer_B0 channel TB0.2, JTAG TDO, TIA0 positive input TRI0+, ADC input A7, and VREF+ reference output (ground referenced). |
| 11 | P1.6 / UCA0RXD / UCA0SOMI / TB0.1 / TDI / TCLK / A6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 UART receive or SPI SOMI, Timer_B0 channel TB0.1, JTAG TDI/TCLK and ADC input A6; TI recommends disabling the pin interrupt while in JTAG debug. |
| 12 | TRI0- | input | Dedicated low-leakage TIA0 negative input pad that exists only in the TSSOP-16 package, with leakage reduced to 5 pA; leave open if unused (the pin is then a high-impedance output). |
| 13 | P1.5/UCA0CLK/TMS/TRI0O/A5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 clock, JTAG TMS, TIA0 output TRI0O and ADC input A5. |
| 14 | P1.4/UCA0STE/TCK/OA0+/A4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_A0 slave transmit enable, JTAG TCK, SAC0 op-amp positive input OA0+ and ADC input A4. |
| 15 | P1.3/UCB0SOMI/UCB0SCL/OA0O/A3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 SPI SOMI or I2C SCL, SAC0 op-amp output OA0O and ADC input A3. |
| 16 | P1.2 / UCB0SIMO / UCB0SDA / TB0TRG / OA0- / A2 / Veref- | bidirectional | General-purpose LVCMOS I/O powered from DVCC (reset default OFF after BOR), multiplexed with eUSCI_B0 SPI SIMO or I2C SDA, Timer_B0 external trigger TB0TRG, SAC0 op-amp negative input OA0-, ADC input A2 and ADC negative reference Veref-. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Embedded Processors & Controllers |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
MSP430FR2310IPW16R - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
msp430fr2310ipw16r-etched.step/msp430fr2310ipw16r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2310ipw16r.step/msp430fr2310ipw16r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (99 pp, sha256
ace23ae4fc6ae702, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).