component
MSP430FR2155TRSMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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<pin name="P1.1/UCB0CLK/ACLK/COMP0.1/A1" x="-17.78" y="20.32" length="middle" direction="io"/>
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<deviceset name="MSP430FR2155TRSMR" prefix="U">
<description></description>
<gates>
<gate name="G$1" symbol="MSP430FR2155TRSMR" x="0" y="0"/>
</gates>
<devices>
<device name="" package="QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm">
<connects>
<connect gate="G$1" pin="P1.1/UCB0CLK/ACLK/COMP0.1/A1" pad="1"/>
<connect gate="G$1" pin="P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+" pad="2"/>
<connect gate="G$1" pin="TEST/SBWTCK" pad="3"/>
<connect gate="G$1" pin="RST/NMI/SBWTDIO" pad="4"/>
<connect gate="G$1" pin="DVCC" pad="5"/>
<connect gate="G$1" pin="DVSS" pad="6"/>
<connect gate="G$1" pin="P2.7/TB0CLK/XIN" pad="7"/>
<connect gate="G$1" pin="P2.6/MCLK/XOUT" pad="8"/>
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<connect gate="G$1" pin="P2.4/COMP1.1" pad="10"/>
<connect gate="G$1" pin="P4.7/UCB1SCL" pad="11"/>
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<connect gate="G$1" pin="P4.2/UCA1RXD/UCA1SOMI" pad="14"/>
<connect gate="G$1" pin="P4.1/UCA1CLK" pad="15"/>
<connect gate="G$1" pin="P4.0/UCA1STE/ISOTXD/ISORXD" pad="16"/>
<connect gate="G$1" pin="P2.1/TB1.2/COMP1.O" pad="17"/>
<connect gate="G$1" pin="EP" pad="33"/>
<connect gate="G$1" pin="P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/Veref-" pad="32"/>
<connect gate="G$1" pin="P1.3/UCB0SOMI/UCB0SCL/A3" pad="31"/>
<connect gate="G$1" pin="P3.0/MCLK" pad="30"/>
<connect gate="G$1" pin="P3.1" pad="29"/>
<connect gate="G$1" pin="P3.2" pad="28"/>
<connect gate="G$1" pin="P3.3" pad="27"/>
<connect gate="G$1" pin="P3.4/SMCLK" pad="26"/>
<connect gate="G$1" pin="P3.5" pad="25"/>
<connect gate="G$1" pin="P3.6" pad="24"/>
<connect gate="G$1" pin="P3.7" pad="23"/>
<connect gate="G$1" pin="P1.4/UCA0STE/TCK/A4" pad="22"/>
<connect gate="G$1" pin="P1.5/UCA0CLK/TMS/A5" pad="21"/>
<connect gate="G$1" pin="P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6" pad="20"/>
<connect gate="G$1" pin="P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+" pad="19"/>
<connect gate="G$1" pin="P2.0/TB1.1/COMP0.O" pad="18"/>
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<technologies><technology name=""/></technologies>
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