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MSP430FR2155TRSMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2155TRSMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(4x4)
MSP430FR2155TRSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1/UCB0CLK/ACLK/COMP0.1/A1 | bidirectional | Port 1 Pin 1: General-purpose I/O with auxiliary clock output, eUSCI_B0 clock input, comparator positive input, and analog input A1 functions selectable via P1SEL register bits. |
| 2 | P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+ | bidirectional | Port 1 Pin 0: General-purpose I/O with subsystem master clock output, eUSCI_B0 slave transmit enable, comparator input, and ADC reference voltage positive input (Veref+) selectable via P1SEL register bits. |
| 3 | TEST/SBWTCK | input | Test mode input pin for JTAG or Spy-Bi-Wire interface clock (SBWTCK); requires internal pulldown (always enabled). |
| 4 | RST/NMI/SBWTDIO | bidirectional | Reset input (active low) or non-maskable interrupt input; also Spy-Bi-Wire data I/O (SBWTDIO); 47-kΩ internal pullup available. |
| 5 | DVCC | power_in | Digital power supply voltage (1.8 V to 3.6 V); requires 10-µF bulk capacitor and 100-nF ceramic bypass capacitor placed within few millimeters. |
| 6 | DVSS | power_in | Digital ground (0 V reference); connect thermal pad to VSS for proper heat dissipation. |
| 7 | P2.7/TB0CLK/XIN | bidirectional | Port 2 Pin 7: General-purpose I/O with Timer_B0 clock input and external low-frequency crystal oscillator input (32 kHz) selectable via P2SEL register bits. |
| 8 | P2.6/MCLK/XOUT | bidirectional | Port 2 Pin 6: General-purpose I/O with main clock (MCLK) output and external low-frequency crystal oscillator output selectable via P2SEL register bits. |
| 9 | P2.5/COMP1.0 | bidirectional | Port 2 Pin 5: General-purpose I/O with enhanced comparator 1 positive input selectable via P2SEL register bits. |
| 10 | P2.4/COMP1.1 | bidirectional | Port 2 Pin 4: General-purpose I/O with enhanced comparator 1 negative input selectable via P2SEL register bits. |
| 11 | P4.7/UCB1SCL | bidirectional | Port 4 Pin 7: General-purpose I/O with eUSCI_B1 I2C serial clock (SCL) or SPI serial clock input selectable via P4SEL register bits. |
| 12 | P4.6/UCB1SDA | bidirectional | Port 4 Pin 6: General-purpose I/O with eUSCI_B1 I2C serial data (SDA) or SPI master in/slave out selectable via P4SEL register bits. |
| 13 | P4.3/UCA1TXD/UCA1SIMO | bidirectional | Port 4 Pin 3: General-purpose I/O with eUSCI_A1 transmit data output or SPI serial data in/master out selectable via P4SEL register bits. |
| 14 | P4.2/UCA1RXD/UCA1SOMI | bidirectional | Port 4 Pin 2: General-purpose I/O with eUSCI_A1 receive data input or SPI serial data out/master in selectable via P4SEL register bits. |
| 15 | P4.1/UCA1CLK | bidirectional | Port 4 Pin 1: General-purpose I/O with eUSCI_A1 serial clock input/output selectable via P4SEL register bits. |
| 16 | P4.0/UCA1STE/ISOTXD/ISORXD | bidirectional | Port 4 Pin 0: General-purpose I/O with eUSCI_A1 slave transmit enable, or isolated data transmit/receive selectable via P4SEL register bits. |
| 17 | P2.1/TB1.2/COMP1.O | bidirectional | Port 2 Pin 1: General-purpose I/O with Timer_B1 capture/compare register output, or enhanced comparator 1 output selectable via P2SEL register bits. |
| 18 | P2.0/TB1.1/COMP0.O | bidirectional | Port 2 Pin 0: General-purpose I/O with Timer_B1 capture/compare register output, or enhanced comparator 0 output selectable via P2SEL register bits. |
| 19 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+ | bidirectional | Port 1 Pin 7: General-purpose I/O with eUSCI_A0 transmit/SPI master in/slave out, Timer_B0 output, JTAG data out, ADC input A7, or 1.2-V reference output selectable via P1SEL register bits. |
| 20 | P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6 | bidirectional | Port 1 Pin 6: General-purpose I/O with eUSCI_A0 receive/SPI slave out, Timer_B0 output, JTAG data in/test clock, and ADC input A6 selectable via P1SEL register bits. |
| 21 | P1.5/UCA0CLK/TMS/A5 | bidirectional | Port 1 Pin 5: General-purpose I/O with eUSCI_A0 serial clock, JTAG test mode select, and ADC input A5 selectable via P1SEL register bits. |
| 22 | P1.4/UCA0STE/TCK/A4 | bidirectional | Port 1 Pin 4: General-purpose I/O with eUSCI_A0 slave transmit enable, JTAG test clock, and ADC input A4 selectable via P1SEL register bits. |
| 23 | P3.7 | bidirectional | Port 3 Pin 7: General-purpose I/O with selectable alternate function via P3SEL register bits. |
| 24 | P3.6 | bidirectional | Port 3 Pin 6: General-purpose I/O with selectable alternate function via P3SEL register bits. |
| 25 | P3.5 | bidirectional | Port 3 Pin 5: General-purpose I/O with selectable alternate function via P3SEL register bits. |
| 26 | P3.4/SMCLK | bidirectional | Port 3 Pin 4: General-purpose I/O with subsystem master clock (SMCLK) output selectable via P3SEL register bits. |
| 27 | P3.3 | bidirectional | Port 3 Pin 3: General-purpose I/O with selectable alternate function via P3SEL register bits. |
| 28 | P3.2 | bidirectional | Port 3 Pin 2: General-purpose I/O with selectable alternate function via P3SEL register bits. |
| 29 | P3.1 | bidirectional | Port 3 Pin 1: General-purpose I/O with selectable alternate function via P3SEL register bits. |
| 30 | P3.0/MCLK | bidirectional | Port 3 Pin 0: General-purpose I/O with main clock (MCLK) output selectable via P3SEL register bits. |
| 31 | P1.3/UCB0SOMI/UCB0SCL/A3 | bidirectional | Port 1 Pin 3: General-purpose I/O with eUSCI_B0 slave out/master in or I2C serial clock, and ADC input A3 selectable via P1SEL register bits. |
| 32 | P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/Veref- | bidirectional | Port 1 Pin 2: General-purpose I/O with eUSCI_B0 master in/slave out or I2C serial data, Timer_B0 external trigger, ADC input A2, or reference voltage negative input selectable via P1SEL register bits. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430FR2155TRSMR - Footprint:
Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm - 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
msp430fr2155trsmr-etched.step/msp430fr2155trsmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2155trsmr.step/msp430fr2155trsmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (146 pp, sha256
20e2c81ab11138f8, retrieved 2026-09-30, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).