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MSP430F67641AIPN

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F67641AIPN

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430F67641AIPN from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD0P0 input SD24_B converter 0 positive analog input; a protection diode is connected to VCC on SD24_B inputs but none to VSS.
2 SD0N0 input SD24_B converter 0 negative analog input; a protection diode is connected to VCC on SD24_B inputs but none to VSS.
3 SD1P0 input SD24_B converter 1 positive analog input; a protection diode is connected to VCC on SD24_B inputs but none to VSS.
4 SD1N0 input SD24_B converter 1 negative analog input; a protection diode is connected to VCC on SD24_B inputs but none to VSS.
5 SD2P0 input SD24_B converter 2 positive analog input; a protection diode is connected to VCC on SD24_B inputs but none to VSS.
6 SD2N0 input SD24_B converter 2 negative analog input; a protection diode is connected to VCC on SD24_B inputs but none to VSS.
7 VREF power_in Analog reference voltage pin powered from AVCC; the provided text gives no further electrical limit for this pin.
8 AVSS power_in Analog ground; AVSS must be at the same potential as DVSS and VSS (0 V).
9 AVCC power_in Analog supply for analog modules, operating from 1.8 V to 3.6 V; TI recommends the same source as DVCC with at most 0.3 V difference.
10 VASYS power_in Analog system supply pin listed as a power pin; the provided text gives no further electrical limit for it.
11 P1.0/PM_TA0.0/VeREF-/A2 bidirectional General-purpose I/O P1.0 with port interrupt (reset default, LVCMOS on DVCC, high-impedance after BOR); alternates are Timer TA0 CCR0 (PM_TA0.0), external ADC reference VeREF- and analog input A2.
12 P1.1/PM_TA0.1/VeREF+/A1 bidirectional General-purpose I/O P1.1 with port interrupt (reset default, LVCMOS on DVCC, high-impedance after BOR); alternates are Timer TA0 CCR1 (PM_TA0.1), external ADC reference VeREF+ and analog input A1.
13 P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 bidirectional General-purpose I/O P1.2 with port interrupt (reset default, LVCMOS on DVCC); alternates are eUSCI_A0 UART RXD or SPI SOMI and analog input A0.
14 P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 bidirectional General-purpose I/O P1.3 with port interrupt (reset default, LVCMOS on DVCC); alternates are eUSCI_A0 UART TXD or SPI SIMO and LCD voltage R03.
15 AUXVCC2 power_in Auxiliary supply 2; maximum load 20 mA for core and I/O and 5 mA for analog modules.
16 AUXVCC1 power_in Auxiliary supply 1; maximum load 20 mA for core and I/O and 5 mA for analog modules; device can start from the higher of primary supply or AUXVCC1.
17 VDSYS power_in Digital system supply pin that must be connected externally on the board for proper device operation.
18 DVCC power_in Digital supply voltage, 1.8 V to 3.6 V over the recommended VCC range; maximum load 20 mA for core and I/O.
19 DVSS power_in Digital ground; all voltages are referenced to VSS = VDVSS = VAVSS.
20 VCORE power_out Internal core-voltage node for internal device use only; no external DC load or voltage may be applied, with 470 nF recommended capacitor.
21 XIN input Input terminal for the crystal oscillator; unused dedicated XIN pins should be connected to DVSS.
22 XOUT output Output terminal for the crystal oscillator; left open when unused.
23 AUXVCC3 power_in Dedicated supply for the backup subsystem (XT1 oscillator, RTC and backup RAM), which is retained during LPM3.5.
24 P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 bidirectional General-purpose I/O P1.4 with port interrupt (reset default, LVCMOS on DVCC); alternates are eUSCI_A1 UART RXD or SPI SOMI, LCD reference LCDREF and LCD voltage R13.
25 P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 bidirectional General-purpose I/O P1.5 with port interrupt (reset default, LVCMOS on DVCC); alternates are eUSCI_A1 UART TXD or SPI SIMO and LCD voltage R23.
26 LCDCAP/R33 bidirectional LCD capacitor/voltage pin (analog, AVCC); must be connected to DVSS if not used.
27 COM0 output LCD common output COM0 (LVCMOS on DVCC, reset state OFF).
28 COM1 output LCD common output COM1 (LVCMOS on DVCC, reset state OFF).
29 COM2 output LCD common output COM2 (LVCMOS on DVCC, reset state OFF).
30 COM3 output LCD common output COM3 (LVCMOS on DVCC, reset state OFF).
31 P1.6/PM_UCA0CLK/COM4 bidirectional General-purpose I/O P1.6 with port interrupt (reset default, LVCMOS on DVCC); alternates are eUSCI_A0 clock and LCD common output COM4.
32 P1.7/PM_UCB0CLK/COM5 bidirectional General-purpose I/O P1.7 with port interrupt (reset default, LVCMOS on DVCC); alternates are eUSCI_B0 clock and LCD common output COM5.
33 P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39 bidirectional General-purpose I/O P2.0 (reset default, LVCMOS on DVCC); alternates are eUSCI_B0 SPI SOMI or I2C SCL, LCD common output COM6 and LCD segment S39.
34 P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38 bidirectional General-purpose I/O P2.1 (reset default, LVCMOS on DVCC); alternates are eUSCI_B0 SPI SIMO or I2C SDA, LCD common output COM7 and LCD segment S38.
35 P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37 bidirectional General-purpose I/O P2.2 (reset default, LVCMOS on DVCC); alternates are eUSCI_A2 UART RXD or SPI SOMI and LCD segment S37.
36 P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36 bidirectional General-purpose I/O P2.3 (reset default, LVCMOS on DVCC); alternates are eUSCI_A2 UART TXD or SPI SIMO and LCD segment S36.
37 P2.4/PM_UCA1CLK/S35 bidirectional General-purpose I/O P2.4 (reset default, LVCMOS on DVCC); alternates are eUSCI_A1 clock and LCD segment S35.
38 P2.5/PM_UCA2CLK/S34 bidirectional General-purpose I/O P2.5 (reset default, LVCMOS on DVCC); alternates are eUSCI_A2 clock and LCD segment S34.
39 P2.6/PM_TA1.0/S33 bidirectional General-purpose I/O P2.6 (reset default, LVCMOS on DVCC); alternates are Timer TA1 CCR0 and LCD segment S33.
40 P2.7/PM_TA1.1/S32 bidirectional General-purpose I/O P2.7 (reset default, LVCMOS on DVCC); alternates are Timer TA1 CCR1 and LCD segment S32.
41 P3.0/PM_TA2.0/S31/BSL_TX bidirectional General-purpose I/O P3.0 (reset default, LVCMOS on DVCC); alternates are Timer TA2 CCR0, LCD segment S31 and bootloader transmit BSL_TX.
42 P3.1/PM_TA2.1/S30/BSL_RX bidirectional General-purpose I/O P3.1 (reset default, LVCMOS on DVCC); alternates are Timer TA2 CCR1, LCD segment S30 and bootloader receive BSL_RX.
43 P3.2/PM_TACLK/PM_RTCCLK/S29 bidirectional General-purpose I/O P3.2 (reset default, LVCMOS on DVCC); alternates are Timer_A clock input TACLK, RTC clock output RTCCLK and LCD segment S29.
44 P3.3/PM_TA0.2/S28 bidirectional General-purpose I/O P3.3 (reset default, LVCMOS on DVCC); alternates are Timer TA0 CCR2 and LCD segment S28.
45 P3.4/PM_SDCLK/S27 bidirectional General-purpose I/O P3.4 (reset default, LVCMOS on DVCC); alternates are SD24_B bit-stream clock SDCLK and LCD segment S27.
46 P3.5/PM_SD0DIO/S26 bidirectional General-purpose I/O P3.5 (reset default, LVCMOS on DVCC); alternates are SD24_B converter 0 bit-stream data SD0DIO and LCD segment S26.
47 P3.6/PM_SD1DIO/S25 bidirectional General-purpose I/O P3.6 (reset default, LVCMOS on DVCC); alternates are SD24_B converter 1 bit-stream data SD1DIO and LCD segment S25.
48 P3.7/PM_SD2DIO/S24 bidirectional General-purpose I/O P3.7 (reset default, LVCMOS on DVCC); alternates are SD24_B converter 2 bit-stream data SD2DIO and LCD segment S24.
49 P4.0/S23 bidirectional General-purpose I/O P4.0 (reset OFF, LVCMOS on DVCC) or LCD segment output S23, selected by P4SEL and LCDS23.
50 P4.1/S22 bidirectional General-purpose I/O P4.1 (reset OFF, LVCMOS on DVCC) or LCD segment output S22, selected by P4SEL and LCDS22.
51 P4.2/S21 bidirectional General-purpose I/O P4.2 (reset OFF, LVCMOS on DVCC) or LCD segment output S21, selected by P4SEL and LCDS21.
52 P4.3/S20 bidirectional General-purpose I/O P4.3 (reset OFF, LVCMOS on DVCC) or LCD segment output S20, selected by P4SEL and LCDS20.
53 P4.4/S19 bidirectional General-purpose I/O P4.4 (reset OFF, LVCMOS on DVCC) or LCD segment output S19, selected by P4SEL and LCDS19.
54 P4.5/S18 bidirectional General-purpose I/O P4.5 (reset OFF, LVCMOS on DVCC) or LCD segment output S18, selected by P4SEL and LCDS18.
55 P4.6/S17 bidirectional General-purpose I/O P4.6 (reset OFF, LVCMOS on DVCC) or LCD segment output S17, selected by P4SEL and LCDS17.
56 P4.7/S16 bidirectional General-purpose I/O P4.7 (reset OFF, LVCMOS on DVCC) or LCD segment output S16, selected by P4SEL and LCDS16.
57 P5.0/S15 bidirectional General-purpose I/O P5.0 (reset OFF, LVCMOS on DVCC) or LCD segment output S15, selected by P5SEL and LCDS15.
58 P5.1/S14 bidirectional General-purpose I/O P5.1 (reset OFF, LVCMOS on DVCC) or LCD segment output S14, selected by P5SEL and LCDS14.
59 DVSYS power_in Digital system pin that must be connected externally on the board for proper device operation.
60 DVSS power_in Digital ground; all voltages are referenced to VSS = VDVSS = VAVSS.
61 P5.2/S13 bidirectional General-purpose I/O P5.2 (reset OFF, LVCMOS on DVCC) or LCD segment output S13, selected by P5SEL and LCDS13.
62 P5.3/S12 bidirectional General-purpose I/O P5.3 (reset OFF, LVCMOS on DVCC) or LCD segment output S12, selected by P5SEL and LCDS12.
63 P5.4/S11 bidirectional General-purpose I/O P5.4 (reset OFF, LVCMOS on DVCC) or LCD segment output S11, selected by P5SEL and LCDS11.
64 P5.5/S10 bidirectional General-purpose I/O P5.5 (reset OFF, LVCMOS on DVCC) or LCD segment output S10, selected by P5SEL and LCDS10.
65 P5.6/S9 bidirectional General-purpose I/O P5.6 (reset OFF, LVCMOS on DVCC) or LCD segment output S9, selected by P5SEL and LCDS9.
66 P5.7/S8 bidirectional General-purpose I/O P5.7 (reset OFF, LVCMOS on DVCC) or LCD segment output S8, selected by P5SEL and LCDS8.
67 P6.0/S7 bidirectional General-purpose I/O P6.0 (reset OFF, LVCMOS on DVCC) or LCD segment output S7, selected by P6SEL and LCDS7.
68 P6.1/S6 bidirectional General-purpose I/O P6.1 (reset OFF, LVCMOS on DVCC) or LCD segment output S6, selected by P6SEL and LCDS6.
69 P6.2/S5 bidirectional General-purpose I/O P6.2 (reset OFF, LVCMOS on DVCC) or LCD segment output S5, selected by P6SEL and LCDS5.
70 P6.3/S4 bidirectional General-purpose I/O P6.3 (reset OFF, LVCMOS on DVCC) or LCD segment output S4, selected by P6SEL and LCDS4.
71 P6.4/S3 bidirectional General-purpose I/O P6.4 (reset OFF, LVCMOS on DVCC) or LCD segment output S3, selected by P6SEL and LCDS3.
72 P6.5/S2 bidirectional General-purpose I/O P6.5 (reset OFF, LVCMOS on DVCC) or LCD segment output S2, selected by P6SEL and LCDS2.
73 P6.6/S1 bidirectional General-purpose I/O P6.6 (reset OFF, LVCMOS on DVCC) or LCD segment output S1, selected by P6SEL and LCDS1.
74 P6.7/S0 bidirectional General-purpose I/O P6.7 (reset OFF, LVCMOS on DVCC) or LCD segment output S0, selected by P6SEL and LCDS0.
75 TEST/SBWTCK input Test mode pin that selects digital I/O on the JTAG pins; it always has an internal pulldown enabled and carries Spy-Bi-Wire clock SBWTCK.
76 PJ.0/SMCLK/TDO bidirectional General-purpose I/O PJ.0 (reset OFF) with SMCLK output or JTAG TDO output; unused pin should be set to port output direction.
77 PJ.1/MCLK/TDI/TCLK bidirectional General-purpose I/O PJ.1 (reset OFF) with MCLK output or JTAG TDI/TCLK input; when used as JTAG pin it should remain open.
78 PJ.2/ADC10CLK/TMS bidirectional General-purpose I/O PJ.2 (reset OFF) with ADC10CLK output or JTAG TMS input; pullups are activated automatically on TMS in JTAG mode.
79 PJ.3/ACLK/TCK bidirectional General-purpose I/O PJ.3 (reset OFF) with ACLK output or JTAG TCK input; pullups are activated automatically on TCK in JTAG mode.
80 RST/NMI/SBWTDIO input Active-low reset input with internal pullup enabled after BOR; also nonmaskable interrupt input NMI and Spy-Bi-Wire data I/O SBWTDIO.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: MSP430F67641AIPN
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: msp430f67641aipn-etched.step / msp430f67641aipn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f67641aipn.step / msp430f67641aipn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (161 pp, sha256 4f4b60167e8688ea, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF