component
MR25H40CDF
Public Made by Adomby adom
Everspin Tech SRAM, DFN-8-EP(5x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MR25H40CDF
Everspin Tech · SRAM · DFN-8-EP(5x6)
MR25H40CDF from Everspin Tech, in a DFN-8-EP(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Active-low chip select; when high the memory is powered down to minimize standby power, inputs are ignored and SO is Hi-Z. |
| 2 | SO | tri_state | Serial data output driven during a read operation and Hi-Z at all other times and when HOLD is low; data transitions on the falling edge of SCK. |
| 3 | WP | input | Write protect; a low on this input prevents write operations to the Status Register. |
| 4 | VSS | power_in | Power supply ground pin. |
| 5 | SI | input | Serial data input sampled on the rising edge of SCK and ignored at other times; can be tied to SO to form a single bidirectional data bus. |
| 6 | SCK | input | Serial clock that synchronizes the MRAM, up to 50 MHz; inputs captured on the rising edge, outputs change on the falling edge, supports SPI Mode 0 and Mode 3. |
| 7 | HOLD | input | A low suspends the current memory operation and the device ignores CS and SCK transitions; all HOLD transitions must occur while CS is low. |
| 8 | VDD | power_in | Power supply voltage from +3.0 to +3.6 volts. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everspin Tech |
| Package | DFN-8-EP(5x6) |
| Category | Memory |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.5 | 4 | V | 15 | ||
| Voltage on any pin | VIN | -0.5 | V | max printed as VDD + 0.5 V | 15 | ||
| Output current per pin | IOUT | -20 | 20 | mA | printed ±20 | 15 | |
| Package power dissipation | PD | 0.6 | W | 15 | |||
| Temperature under bias | TBIAS | -45 | 95 | °C | Industrial | 15 | |
| Storage temperature | Tstg | -55 | 150 | °C | 15 | ||
| Lead temperature during solder | TLead | 260 | °C | 3 minute max | 15 | ||
| Maximum magnetic field during write | Hmax_write | 12000 | A/m | Write | 15 | ||
| Maximum magnetic field during read or standby | Hmax_read | 12000 | A/m | Read or Standby | 15 | ||
| Power supply voltage | VDD | 3 | 3.6 | V | 16 | ||
| Input high voltage | VIH | 2.2 | V | max printed as VDD + 0.3 V | 16 | ||
| Input low voltage | VIL | -0.5 | 0.8 | V | 16 | ||
| Ambient temperature under bias | TA | -40 | 85 | °C | Industrial | 16 | |
| Input leakage current | ILI | -1 | 1 | µA | printed ±1 | 16 | |
| Output leakage current | ILO | -1 | 1 | µA | printed ±1 | 16 | |
| Output low voltage | VOL | 0.4 | V | IOL = +4 mA | 16 | ||
| Output high voltage | VOH | 2.4 | V | IOH = -4 mA | 16 | ||
| Active read current | IDDR | 5 | 11 | mA | @ 1 MHz | 17 | |
| Active read current | IDDR | 12 | 17 | mA | @ 40 MHz | 17 | |
| Active write current | IDDW | 9 | 25 | mA | @ 1 MHz | 17 | |
| Active write current | IDDW | 28 | 42 | mA | @ 40 MHz | 17 | |
| AC standby current (CS high) | ISB1 | 250 | 400 | µA | @ 40 MHz | 17 | |
| CMOS standby current (CS high) | ISB2 | 90 | 180 | µA | 17 | ||
| Standby sleep mode current (CS high) | IZZ | 15 | 40 | µA | 17 | ||
| Control input capacitance | CIn | 6 | pF | f = 1.0 MHz, dV = 3.0 V, TA = 25 °C | 18 | ||
| Input/Output capacitance | CI/O | 8 | pF | f = 1.0 MHz, dV = 3.0 V, TA = 25 °C | 18 |
CAD (KiCad official)
- Symbol:
MR25H40CDF - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN-8-EP(5x6) (KiCad packages3D, STEP)
- 3D model files:
mr25h40cdf-etched.step/mr25h40cdf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mr25h40cdf.step/mr25h40cdf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Everspin Tech datasheet (30 pp, sha256
a9e4056e58de94e6, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MR25H40CDF
**Everspin Tech** · SRAM · DFN-8-EP(5x6)
MR25H40CDF from Everspin Tech, in a DFN-8-EP(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Active-low chip select; when high the memory is powered down to minimize standby power, inputs are ignored and SO is Hi-Z. |
| 2 | SO | tri_state | Serial data output driven during a read operation and Hi-Z at all other times and when HOLD is low; data transitions on the falling edge of SCK. |
| 3 | WP | input | Write protect; a low on this input prevents write operations to the Status Register. |
| 4 | VSS | power_in | Power supply ground pin. |
| 5 | SI | input | Serial data input sampled on the rising edge of SCK and ignored at other times; can be tied to SO to form a single bidirectional data bus. |
| 6 | SCK | input | Serial clock that synchronizes the MRAM, up to 50 MHz; inputs captured on the rising edge, outputs change on the falling edge, supports SPI Mode 0 and Mode 3. |
| 7 | HOLD | input | A low suspends the current memory operation and the device ignores CS and SCK transitions; all HOLD transitions must occur while CS is low. |
| 8 | VDD | power_in | Power supply voltage from +3.0 to +3.6 volts. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everspin Tech |
| Package | DFN-8-EP(5x6) |
| Category | Memory |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.5 | | 4 | V | | 15 |
| Voltage on any pin | VIN | -0.5 | | | V | max printed as VDD + 0.5 V | 15 |
| Output current per pin | IOUT | -20 | | 20 | mA | printed ±20 | 15 |
| Package power dissipation | PD | | | 0.6 | W | | 15 |
| Temperature under bias | TBIAS | -45 | | 95 | °C | Industrial | 15 |
| Storage temperature | Tstg | -55 | | 150 | °C | | 15 |
| Lead temperature during solder | TLead | | | 260 | °C | 3 minute max | 15 |
| Maximum magnetic field during write | Hmax_write | | | 12000 | A/m | Write | 15 |
| Maximum magnetic field during read or standby | Hmax_read | | | 12000 | A/m | Read or Standby | 15 |
| Power supply voltage | VDD | 3 | | 3.6 | V | | 16 |
| Input high voltage | VIH | 2.2 | | | V | max printed as VDD + 0.3 V | 16 |
| Input low voltage | VIL | -0.5 | | 0.8 | V | | 16 |
| Ambient temperature under bias | TA | -40 | | 85 | °C | Industrial | 16 |
| Input leakage current | ILI | -1 | | 1 | µA | printed ±1 | 16 |
| Output leakage current | ILO | -1 | | 1 | µA | printed ±1 | 16 |
| Output low voltage | VOL | | | 0.4 | V | IOL = +4 mA | 16 |
| Output high voltage | VOH | 2.4 | | | V | IOH = -4 mA | 16 |
| Active read current | IDDR | | 5 | 11 | mA | @ 1 MHz | 17 |
| Active read current | IDDR | | 12 | 17 | mA | @ 40 MHz | 17 |
| Active write current | IDDW | | 9 | 25 | mA | @ 1 MHz | 17 |
| Active write current | IDDW | | 28 | 42 | mA | @ 40 MHz | 17 |
| AC standby current (CS high) | ISB1 | | 250 | 400 | µA | @ 40 MHz | 17 |
| CMOS standby current (CS high) | ISB2 | | 90 | 180 | µA | | 17 |
| Standby sleep mode current (CS high) | IZZ | | 15 | 40 | µA | | 17 |
| Control input capacitance | CIn | | | 6 | pF | f = 1.0 MHz, dV = 3.0 V, TA = 25 °C | 18 |
| Input/Output capacitance | CI/O | | | 8 | pF | f = 1.0 MHz, dV = 3.0 V, TA = 25 °C | 18 |
## CAD (KiCad official)
- Symbol: `MR25H40CDF`
- Footprint: `Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm`
- 3D model: DFN-8-EP(5x6) (KiCad packages3D, STEP)
- 3D model files: `mr25h40cdf-etched.step` / `mr25h40cdf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mr25h40cdf.step` / `mr25h40cdf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Everspin Tech datasheet](docs/mr25h40cdf-datasheet.pdf) (30 pp, sha256 `a9e4056e58de94e6`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mr25h40cdf-datasheet.pdf)