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Contents

README

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MMDF1N05ER2G-JSM

JSMSEMI · MOSFETs · SOP-8

MMDF1N05ER2G-JSM from JSMSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S2 passive Source of N-channel MOSFET 2 (VDS max 60 V, ID 6.3 A at TA=25°C).
2 G2 input Gate of N-channel MOSFET 2 (VGS max ±20 V, threshold 1.0 to 3.0 V).
3 S1 passive Source of N-channel MOSFET 1 (VDS max 60 V, ID 6.3 A at TA=25°C).
4 G1 input Gate of N-channel MOSFET 1 (VGS max ±20 V, threshold 1.0 to 3.0 V).
5 D1 passive Drain of MOSFET 1 (VDS max 60 V, pulsed IDM 40 A), tied to pin 6.
6 D1 passive Drain of MOSFET 1 (VDS max 60 V, pulsed IDM 40 A), tied to pin 5.
7 D2 passive Drain of MOSFET 2 (VDS max 60 V, pulsed IDM 40 A), tied to pin 8.
8 D2 passive Drain of MOSFET 2 (VDS max 60 V, pulsed IDM 40 A), tied to pin 7.

Key specifications

Parameter Value
Manufacturer JSMSEMI
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: MMDF1N05ER2G-JSM
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: mmdf1n05er2g-jsm-etched.step / mmdf1n05er2g-jsm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mmdf1n05er2g-jsm.step / mmdf1n05er2g-jsm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: JSMSEMI datasheet (5 pp, sha256 50ce43e8ee7603be, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF