component
MM74HC595MTC
Public Made by Adomby adom
onsemi Shifting Register, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"number": "1",
"name": "QB",
"type": "tri_state",
"description": "Parallel output bit B from the storage register, a 3-state output that goes high-impedance when G is HIGH."
},
{
"number": "2",
"name": "QC",
"type": "tri_state",
"description": "Parallel output bit C from the storage register, a 3-state output that goes high-impedance when G is HIGH."
},
{
"number": "3",
"name": "QD",
"type": "tri_state",
"description": "Parallel output bit D from the storage register, a 3-state output that goes high-impedance when G is HIGH."
},
{
"number": "4",
"name": "QE",
"type": "tri_state",
"description": "Parallel output bit E from the storage register, a 3-state output that goes high-impedance when G is HIGH."
},
{
"number": "5",
"name": "QF",
"type": "tri_state",
"description": "Parallel output bit F from the storage register, a 3-state output that goes high-impedance when G is HIGH."
},
{
"number": "6",
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},
{
"number": "7",
"name": "QH",
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"description": "Parallel output bit H from the storage register, a 3-state output that goes high-impedance when G is HIGH."
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{
"number": "8",
"name": "GND",
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"description": "Ground reference; all device voltages are referenced to this pin."
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{
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"name": "Q'H",
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"description": "Serial data output of the shift register (cascade output) that is forced to 0 when SCLR and G are LOW; it is not part of the 3-state group."
},
{
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},
{
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},
{
"number": "12",
"name": "RCK",
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"description": "Storage register clock, positive-edge triggered, that transfers the shift register contents to the output latches."
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{
"number": "13",
"name": "G",
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"description": "Active-high output enable; when HIGH, QA through QH are forced to the 3-state (high-impedance) condition."
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{
"number": "14",
"name": "SER",
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"description": "Serial data input to the shift register, shifted into bit Q0 on the SCK positive edge."
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{
"number": "15",
"name": "QA",
"type": "tri_state",
"description": "Parallel output bit A from the storage register, a 3-state output that goes high-impedance when G is HIGH."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, recommended range 2 V to 6 V."
}
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"extractor flagged: The pin table on page 4 is the device-level pin definition; the Figure 2 pin configuration drawing i; The datasheet's TSSOP section (page 13, Figure 6) gives only the package outline and dimensions, not; The datasheet is a Fairchild-era document (rev 1.0.2) now distributed by onsemi; the ordering row fo",
"1/16 pin names appear NOWHERE in the datasheet text: [\"9:Q'H@p4\"]"
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{
"name": "Minimum HIGH Level Output Voltage Q'H",
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"name": "Maximum LOW Level Output Voltage Q'H",
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{
"name": "Maximum Input Leakage",
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{
"name": "Maximum 3-State Output Leakage",
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{
"name": "Maximum Quiescent Supply Current",
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{
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{
"name": "Maximum Operating Frequency",
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{
"name": "Maximum Operating Frequency",
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"conditions": "CL=50pF, VCC=6.0V, TA=-40 to 85°C (typ at 25°C)",
"source_page": 8,
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{
"name": "Maximum Propagation Delay, SCK to Q'H",
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"kind": "timing",
"unit": "ns",
"min": null,
"typ": 14,
"max": 53,
"conditions": "CL=50pF, VCC=4.5V, TA=-40 to 85°C (typ at 25°C)",
"source_page": 8,
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{
"name": "Maximum Propagation Delay, RCK to QA thru Q'H",
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"min": null,
"typ": 21,
"max": 44,
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{
"name": "Maximum Output Enable Time from G to QA thru Q'H",
"symbol": "tPZH,tPZL",
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"unit": "ns",
"min": null,
"typ": 15,
"max": 44,
"conditions": "RL=1kΩ, CL=50pF, VCC=4.5V, TA=-40 to 85°C (typ at 25°C)",
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{
"name": "Maximum Output Disable Time from G to QA thru Q'H",
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{
"name": "Minimum Setup Time from SER to SCK",
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"min": null,
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{
"name": "Minimum Removal Time from SCLR to SCK",
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"name": "Minimum Hold Time from SER to SCK",
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{
"name": "Minimum Pulse Width of SCK or SCLR",
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"name": "Maximum Input Capacitance",
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{
"name": "Maximum Output Capacitance",
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