MM74HC595MTC

{
  "slug": "mm74hc595mtc",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Shifting Register, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic ics",
    "mm74hc595mtc",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
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    "path": "docs/hero.png"
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    "mm74hc595mtc.step",
    "mm74hc595mtc.lbr",
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  "component": {
    "mpn": "MM74HC595MTC",
    "manufacturer": "onsemi",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic ICs",
    "subcategory": "Shifting Register",
    "datasheet": "https://www.onsemi.com/pdf/datasheet/mm74hc595mtc-d.pdf",
    "parts": {
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      "lbr": "mm74hc595mtc.lbr"
    },
    "distributor_links": {
      "lcsc": "C274671",
      "digikey": "MM74HC595MTCFS-ND",
      "mouser": "512-MM74HC595MTC"
    },
    "distributor_check": {
      "checked_at": "2026-10-24T00:10:57Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "MM74HC595MTCFS-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "512-MM74HC595MTC",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Parallel output bit B from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Parallel output bit C from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Parallel output bit D from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Parallel output bit E from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Parallel output bit F from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Parallel output bit G from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Parallel output bit H from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference; all device voltages are referenced to this pin."
      },
      {
        "number": "9",
        "name": "Q'H",
        "type": "output",
        "description": "Serial data output of the shift register (cascade output) that is forced to 0 when SCLR and G are LOW; it is not part of the 3-state group."
      },
      {
        "number": "10",
        "name": "SCLR",
        "type": "input",
        "description": "Active-low shift register clear that forces the shift register contents to zero (Q'H = 0 while G is LOW, per the truth table)."
      },
      {
        "number": "11",
        "name": "SCK",
        "type": "input",
        "description": "Shift register clock, positive-edge triggered, with a guaranteed shift frequency of DC to 30 MHz at 5 V."
      },
      {
        "number": "12",
        "name": "RCK",
        "type": "input",
        "description": "Storage register clock, positive-edge triggered, that transfers the shift register contents to the output latches."
      },
      {
        "number": "13",
        "name": "G",
        "type": "input",
        "description": "Active-high output enable; when HIGH, QA through QH are forced to the 3-state (high-impedance) condition."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input to the shift register, shifted into bit Q0 on the SCK positive edge."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Parallel output bit A from the storage register, a 3-state output that goes high-impedance when G is HIGH."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, recommended range 2 V to 6 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin table on page 4 is the device-level pin definition; the Figure 2 pin configuration drawing i; The datasheet's TSSOP section (page 13, Figure 6) gives only the package outline and dimensions, not; The datasheet is a Fairchild-era document (rev 1.0.2) now distributed by onsemi; the ordering row fo",
          "1/16 pin names appear NOWHERE in the datasheet text: [\"9:Q'H@p4\"]"
        ],
        "pages_sent": 16,
        "cost_usd": 0.063,
        "at": "2026-10-24T00:10:43"
      },
      "datasheet": {
        "url": "https://www.onsemi.com/pdf/datasheet/mm74hc595mtc-d.pdf",
        "pages": 16,
        "sha256": "d5478843a2f0d444",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": -0.0,
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}