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MIC5891YN

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Microchip Tech Latches, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MIC5891YN

Microchip Tech · Latches · PDIP-16

MIC5891YN from Microchip Tech, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GROUND power_in Common ground return for the device, and the reference for the logic input low level, which is specified as VSS-0.3V to 0.8V at VDD = 5.0V to 12V.
2 CLOCK input Serial data present at SERIAL DATA IN is shifted into the register on the rising edge of CLOCK, with a minimum clock pulse width of 150 ns and a maximum clock frequency of 3.3 MHz minimum (typically 5 MHz).
3 SERIAL DATA IN input CMOS, PMOS, NMOS and TTL-compatible serial data input, which must be stable before the rising edge of CLOCK; TTL use may require pull-up resistors to ensure a proper logic-high input.
4 STROBE input When held high, the 8 bits in the shift register are transferred to the latches, with a minimum strobe pulse width of 100 ns, and the latches keep accepting new data while STROBE stays high.
5 OUT1 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
6 OUT2 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
7 OUT3 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
8 OUT4 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
9 OUT5 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
10 OUT6 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
11 OUT7 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
12 OUT8 output Open-emitter Darlington output with suppression diode for inductive load transients, capable of sourcing 500 mA and sustaining at least 35 V in the on-state.
13 LOAD SUPPLY (VBB) power_in Load supply for the driver outputs, specified as +5.0 V to +50 V.
14 OUTPUT ENABLE input When low, outputs are controlled by the latch state; when high, all outputs are forced low (disabled) without affecting the shift register or latch data.
15 LOGIC SUPPLY (VDD) power_in Logic supply for the CMOS shift register, latches and control circuitry, specified as +4.5 V to +15 V.
16 SERIAL DATA OUT output CMOS serial data output that allows additional drivers to be cascaded when more than 8 bits are required, with output resistance of 20 kΩ maximum at VDD = 5 V and 6.0 kΩ maximum at VDD = 12 V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Leakage Current ICEX -50 µA TA = +25°C 4
Output Leakage Current ICEX -100 µA TA = +85°C 4
Output Saturation Voltage VCE(SAT) 2.3 V IOUT = -100 mA, TA = +85°C 4
Output Saturation Voltage VCE(SAT) 2.4 V IOUT = -225 mA, TA = +85°C 4
Output Saturation Voltage VCE(SAT) 2.5 V IOUT = -350 mA, TA = +85°C 4
Output Sustaining Voltage VCE(SUS) 35 V IOUT = -350 mA, L = 2 mH 4
Input Voltage HIGH (VDD = 5.0V) VIN(1) 3.5 V VDD = 5.0V 4
Input Voltage HIGH (VDD = 12V) VIN(1) 10.5 V VDD = 12V 4
Input Voltage LOW VIN(0) 0.8 V VDD = 5.0V to 12V 4
Input Current HIGH IIN(1) 120 µA VDD = VIN = 5.0V 4
Input Current HIGH IIN(1) 240 µA VDD = 12V 4
Input Impedance ZIN 100 kΩ VDD = 5.0V 4
Input Impedance ZIN 50 kΩ VDD = 12V 4
Maximum Clock Frequency fc 3.3 MHz 4
Serial Data Output Resistance ROUT 20 kΩ VDD = 5.0V 4
Serial Data Output Resistance ROUT 6 kΩ VDD = 12V 4
Turn-On Delay tPLH 2 µs Output Enable to Output, IOUT = -350 mA 4
Turn-Off Delay tPHL 10 µs Output Enable to Output, IOUT = -350 mA 4
Supply Current (logic-side, all outputs on) IBB 10 mA All outputs on, all outputs open 4
Supply Current (all outputs off) IBB 200 µA All outputs off 4
Logic Supply Current (all outputs off, VDD = 5V) IDD 100 µA VDD = 5V, all outputs off, inputs = 0V 4
Logic Supply Current (all outputs off, VDD = 12V) IDD 200 µA VDD = 12V, all outputs off, inputs = 0V 4
Logic Supply Current (one output on, VDD = 5V) IDD 1 mA VDD = 5V, one output on, inputs = 0V 4
Logic Supply Current (one output on, VDD = 12V) IDD 3 mA VDD = 12V, one output on, inputs = 0V 4
Diode Leakage Current IH 50 µA TA = +25°C; Max. VBB 4
Diode Leakage Current IH 100 µA TA = +85°C; Max. VBB 4
Diode Forward Voltage VF 2 V IF = 350 mA; VBB open 4
Data set-up time before clock pulse 75 ns Reference A, VDD = 5.0V 7
Data hold time after clock pulse 75 ns Reference B, VDD = 5.0V 7
Minimum data pulse width 150 ns Reference C, VDD = 5.0V 7
Minimum clock pulse width 150 ns Reference D, VDD = 5.0V 7
Minimum time between clock activation and strobe 300 ns Reference E, VDD = 5.0V 7
Minimum strobe pulse width 100 ns Reference F, VDD = 5.0V 7
Time between strobe activation and output transition 1 µs Reference G, VDD = 5.0V 7
Logic Supply Voltage Range VDD 4.5 15 V 3
Load Supply Voltage Range VBB 5 50 V 3
Output Voltage VOUT 50 V 3
Input Voltage Range VIN -0.3 V 3
Storage Temperature Range TS -65 150 °C 5
Operating Temperature Range TA -40 85 °C 5
Thermal Resistance, junction to air (PDIP) JA 60 °C/W PDIP package, from Figure 2-1 6

CAD (KiCad official)

  • Symbol: MIC5891YN
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: mic5891yn-etched.step / mic5891yn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mic5891yn.step / mic5891yn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (18 pp, sha256 e155c71f2ce3d38c, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF