component
MCP6V02-E
Public Made by Adomby adom
Microchip Tech Precision OpAmps, DFN-8-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownMCP6V02-E
Microchip Tech · Precision OpAmps · DFN-8-EP(4x4)
MCP6V02-E from Microchip Tech, in a DFN-8-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Op amp A output, a low-impedance voltage source. |
| 2 | VINA- | input | Op amp A inverting input, a high-impedance CMOS input with low bias current. |
| 3 | VINA+ | input | Op amp A non-inverting input, a high-impedance CMOS input with low bias current. |
| 4 | VSS | power_in | Negative power supply, normally connected to ground in single-supply use. |
| 5 | VINB+ | input | Op amp B non-inverting input, a high-impedance CMOS input with low bias current. |
| 6 | VINB- | input | Op amp B inverting input, a high-impedance CMOS input with low bias current. |
| 7 | VOUTB | output | Op amp B output, a low-impedance voltage source. |
| 8 | VDD | power_in | Positive power supply, 1.8V to 5.5V above VSS, and needs bypass capacitors. |
| 9 | EP | power_in | Exposed thermal pad internally connected to VSS and must be connected to the same potential as VSS on the PCB; it can be tied to a ground plane to lower thermal resistance (θJA). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DFN-8-EP(4x4) |
| Category | Operational Amplifier/Comparator |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -2 | 2 | µV | TA = +25°C (Note 1) | 3 | |
| Input Offset Voltage Drift with Temperature (linear Temp. Co.) | TC1 | -50 | 50 | nV/°C | TA = -40 to +125°C (Note 1) | 3 | |
| Power Supply Rejection | PSRR | 130 | 143 | dB | (Note 1) | 3 | |
| Input Bias Current across Temperature | IB | 600 | 5000 | pA | TA = +125°C | 3 | |
| Input Offset Current across Temperature | IOS | -1000 | -75 | 1000 | pA | TA = +125°C | 3 |
| Common-Mode Input Voltage Range | VCMR | -0.2 | 0.2 | V | VSS − 0.20 to VDD + 0.20 (Note 2) | 3 | |
| Common-Mode Rejection | CMRR | 130 | 142 | dB | VDD = 1.8V, VCM = -0.2V to 2.0V (Note 1, Note 2) | 3 | |
| Common-Mode Rejection | CMRR | 140 | 152 | dB | VDD = 5.5V, VCM = -0.2V to 5.7V (Note 1, Note 2) | 3 | |
| DC Open-Loop Gain (large signal) | AOL | 130 | 145 | dB | VDD = 1.8V, VOUT = 0.2V to 1.6V (Note 1) | 3 | |
| DC Open-Loop Gain (large signal) | AOL | 140 | 156 | dB | VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1) | 3 | |
| Maximum Output Voltage Swing | VOL, VOH | 15 | 15 | mV | G = +2, 0.5V input overdrive; VSS + 15 mV min / VDD − 15 mV | 4 | |
| Supply Voltage | VDD | 1.8 | 5.5 | V | 4 | ||
| Quiescent Current per amplifier | IQ | 200 | 300 | 400 | µA | IO = 0 | 4 |
| POR Trip Voltage | VPOR | 1.15 | 1.65 | V | 4 | ||
| Specified Temperature Range | TA | -40 | 125 | °C | 5 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | (Note 1) | 5 | |
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Current at Input Pins | -2 | 2 | mA | 3 | |||
| Current at Output and Supply Pins | -30 | 30 | mA | 3 | |||
| Max. Junction Temperature | TJ | 150 | °C | 3 | |||
| ESD protection (HBM) | 4 | kV | all pins, HBM | 3 | |||
| ESD protection (MM) | 300 | V | all pins, MM | 3 | |||
| Thermal Resistance, 8L-4x4 DFN | θJA | 44 | °C/W | (Note 2) JC51-7 four layer board with ground plane and vias | 5 | ||
| Input Offset Voltage Quadratic Temp. Co. | TC2 | 0.1 | nV/°C² | TA = -40 to +125°C; printed ±0.1 | 3 | ||
| Input Bias Current | IB | 1 | pA | printed ±1 | 3 | ||
| Output Short Circuit Current | ISC | 7 | mA | VDD = 1.8V; printed ±7 | 4 | ||
| Output Short Circuit Current | ISC | 22 | mA | VDD = 5.5V; printed ±22 | 4 | ||
| Gain Bandwidth Product | GBWP | 1.3 | MHz | 4 | |||
| Slew Rate | SR | 0.5 | V/µs | 4 | |||
| Phase Margin | PM | 65 | ° | G = +1 | 4 | ||
| Input Noise Voltage | Eni | 2.5 | µVP-P | f = 0.1 Hz to 10 Hz | 4 | ||
| Input Noise Voltage Density | eni | 120 | nV/√Hz | f < 2.5 kHz | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | gold | SN = Plastic SOIC (150mil Body), 8-lead * Y = nickel palladium gold manufacturing designator. Only | 41 |
CAD (KiCad official)
- Symbol:
MCP6V02-E - Footprint:
Package_DFN_QFN:DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm - 3D model: DFN-8-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
mcp6v02-e-etched.step/mcp6v02-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp6v02-e.step/mcp6v02-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (44 pp, sha256
28cdd67b1fe05611, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).