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MCP4921T-E

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Microchip Tech Digital To Analog Converters (DAC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP4921T-E

Microchip Tech · Digital To Analog Converters (DAC) · SOIC-8

MCP4921T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply voltage input that ranges from 2.7V to 5.5V relative to VSS, with a clean supply and about 0.1 µF ceramic plus 10 µF tantalum bypass capacitors recommended.
2 CS input Active-low chip select input that must be low to enable the serial clock and data functions.
3 SCK input SPI-compatible serial clock input.
4 SDI input SPI-compatible serial data input.
5 LDAC input DAC output synchronization input that, when driven low, transfers the input register contents to the output register and updates VOUT, and can be tied to VSS to update VOUT on the rising edge of CS.
6 VREF power_in Voltage reference input whose input voltage can range from VSS to VDD and which may be tied to VDD.
7 VSS power_in Analog ground pin and current return path that must be connected to a ground plane through a low-impedance connection.
8 VOUT output DAC buffered analog output whose full-scale range is VSS to G×VREF (G = 1x or 2x) and which cannot go higher than VDD.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Voltage VDD 2.7 5.5 V 3
Supply Current IDD 175 350 µA VDD = 5V 3
Supply Current IDD 125 250 µA VDD = 3V 3
Software Shutdown Current ISHDN_SW 3.3 6 µA Power-on Reset circuit remains on 3
Resolution n 12 Bits 3
INL Error INL -12 2 12 LSb 3
DNL DNL -0.75 0.2 0.75 LSb Note 1: guaranteed monotonic by design over all codes 3
Offset Error VOS 0.02 1 % of FSR Code = 0x000h 4
Gain Error gE -0.1 1 % of FSR Code = 0xFFFh, not including offset error 4
Input Range - Buffered Mode VREF 0.04 V Note 2 4
Input Range - Unbuffered Mode VREF 0 V 4
Output Swing VOUT 0.01 V Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD - 40 mV) 4
Short Circuit Current ISC 15 24 mA 4
Schmitt Trigger High Level Input Voltage (all digital inputs) VIH 0.7 VDD 7
Schmitt Trigger Low Level Input Voltage (all digital inputs) VIL 0.2 VDD 7
Input Leakage Current ILEAKAGE -1 1 µA LDAC = CS = SDI = SCK = VREF = VDD or VSS 7
Clock Frequency FCLK 20 MHz TA = +25°C (Note 1) 7
Clock High Time tHI 15 ns Note 1 7
Clock Low Time tLO 15 ns Note 1 7
CS Fall to First Rising CLK Edge tCSSR 40 ns Applies only when CS falls with CLK high (Note 1) 7
Data Input Setup Time tSU 15 ns Note 1 7
Data Input Hold Time tHD 10 ns Note 1 7
SCK Rise to CS Rise Hold Time tCHS 15 ns Note 1 7
CS High Time tCSH 15 ns Note 1 7
LDAC Pulse Width tLD 100 ns Note 1 7
LDAC Setup Time tLS 40 ns Note 1 7
SCK Idle Time before CS Fall tIDLE 40 ns Note 1 7
Specified Temperature Range TA -40 125 °C 8
Operating Temperature Range TA -40 125 °C Note 1 8
Storage Temperature Range TA -65 150 °C 8
Thermal Resistance, 8L-SOIC JA 150 °C/W 8
Supply Voltage (VDD) absolute maximum VDD 6.5 V 3
Voltage on all inputs and outputs w.r.t VSS -0.3 V w.r.t VSS; upper limit printed as VDD + 0.3V 3
Current at Input Pins -2 2 mA 3
Current at Supply Pins -50 50 mA 3
Current at Output Pins -25 25 mA 3
Storage Temperature -65 150 °C 3
Ambient Temperature with Power Applied -55 125 °C 3
Maximum Junction Temperature TJ 150 °C 3
ESD Protection (HBM) 4 kV HBM 3
ESD Protection (MM) 400 V MM 3
Input Voltage (extended temperature table) VDD 2.7 5.5 V Extended table, TA = +125°C 5
Resolution (extended temperature table) n 12 Bits Extended table, TA = +125°C 5
INL Error (extended temperature table) INL -4 4 LSb Extended table, TA = +125°C; printed as ±4 LSb 5
DNL (extended temperature table) DNL -0.25 0.25 LSb Extended table, TA = +125°C; Note 1; printed as ±0.25 LSb 5
Offset Error (extended temperature table) VOS -0.02 0.02 % of FSR Extended table, TA = +125°C; Code = 0x000h; printed as ±0.02 5
Input Range - Unbuffered Mode (extended temperature table) VREF 0 V Extended table, TA = +125°C 5
Output Swing (extended temperature table) VOUT 0.01 V Extended table, TA = +125°C; accuracy is better than 1 LSb for VOUT = 10 mV to (VDD - 40 mV) 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin MS = 8-Lead Plastic Micro Small Outline (MSOP) SN = 8-Lead Plastic Small Outline - Narrow, 150 mil 47

CAD (KiCad official)

  • Symbol: MCP4921T-E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mcp4921t-e-etched.step / mcp4921t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4921t-e.step / mcp4921t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (50 pp, sha256 a52733deb49e0ae4, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF