by adom

Microchip Tech Digital To Analog Converters (DACs), DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

History Download

Ray Publish 0.1.0 2acccf2 7d ago

MCP47CVB12-E

Microchip Tech · Digital To Analog Converters (DACs) · DFN-10-EP(3x3)

MCP47CVB12-E from Microchip Tech, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Positive supply voltage pin, 2.7V to 5.5V for full specifications (1.8V to 2.7V reduced), with about 0.1 µF ceramic bypass recommended close to the pin.
2	A0	input	I2C slave address bit 0 pin (Schmitt Trigger input) that sets the lowest bit of the 7-bit slave address.
3	VREF	power_in	Analog voltage reference input (buffered or unbuffered) or output when the internal band gap is selected; disconnected when VDD is the reference.
4	VOUT0	output	Buffered analog voltage output of DAC0, with about 1 Ω DC impedance in normal mode and 1 kΩ, 100 kΩ or open in power-down.
5	VOUT1	output	Buffered analog voltage output of DAC1, with about 1 Ω DC impedance in normal mode and 1 kΩ, 100 kΩ or open in power-down.
6	LAT/HVC	input	Latch pin that transfers volatile wiper and configuration values to both DAC outputs when taken to VIL, and high-voltage command pin for MTP programming (7.5V, at least 6.4 mA, above 5.5V only during programming).
7	VSS	power_in	Ground reference pin for all circuitry on the device, to be connected to a low-impedance ground plane.
8	A1	input	I2C slave address bit 1 pin (Schmitt Trigger input) that sets the second-lowest bit of the 7-bit slave address.
9	SCL	input	I2C serial clock input (Schmitt Trigger) supporting Standard 100 kHz, Fast 400 kHz and High-Speed up to 3.4 MHz modes.
10	SDA	bidirectional	I2C serial data input/output (Schmitt Trigger) with slope-controlled output driver.
11	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	DFN-10-EP(3x3)
Category	ADC/DAC/Data Conversion
Pins	11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage	VDD	2.7		5.5	V	Full specifications	6
Supply Voltage (reduced)	VDD	1.8		2.7	V	DAC operation (reduced analog specifications) and serial interface	6
Operating Temperature	TA	-40		125	°C	Extended	6
Voltage on VDD	VDD	-0.6		6.5	V	with respect to VSS	5
Input clamp current	IIK	-20		20	mA	VI < 0, VI > VDD, VI > VPP on HV pins	5
Output clamp current	IOK	-20		20	mA	VO < 0 or VO > VDD	5
Max current out of VSS pin				100	mA	Dual	5
Max current into VDD pin				100	mA	Dual	5
Max current sourced by VOUT pin				20	mA		5
Max current sunk by VOUT pin				20	mA		5
Total power dissipation				400	mW		5
Storage temperature		-65		150	°C		5
Ambient temperature with power applied		-55		125	°C		5
Maximum Junction Temperature	TJ			150	°C		5
Soldering temperature of leads				300	°C	10 seconds	5
ESD HBM				6	kV	all pins	5
Power-on Reset VDD (rising)	VPOR			1.75	V	VDD voltages greater than the VPOR limit ensure that the device is out of Reset	6
Brown-out Reset VDD (falling)	VBOR			1.61	V	RAM retention voltage: (VRAM)<VBOR	6
Power-on Reset to Output-Driven Delay	TPOR2OD			145	µs	VDD rising, VDD >VPOR, dual output	6
Supply Current, dual, 100 kHz	IDD			330	µA	Dual 100 kHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale	7
Supply Current, dual, 400 kHz	IDD			410	µA	Dual 400 kHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale	7
Supply Current, dual, 1.7 MHz	IDD			560	µA	Dual 1.7 MHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale	7
Supply Current, dual, 3.4 MHz	IDD			720	µA	Dual 3.4 MHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale	7
Supply Current, dual, interface inactive	IDD			280	µA	Dual, serial interface inactive, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale	7
Power-Down Current	IDDP		0.65	3.8	µA	PDxB:PDxA = 01, VRxB:VRxA = 10, VOUT not connected	7
Resistor Ladder Resistance	RL	63.9	71	78.1	kΩ	VRxB:VRxA = 10, VREF = VDD	8
Nominal VOUT Match			0.016	0.3	%	1.8V ≤ VDD ≤ 5.5V	8
VOUT Tempco	ΔVOUT/ΔT		3		ppm/°C	Code = Mid-Scale, VRxB:VRxA = 00, 10 and 11	8
Zero-Scale Error, 10-bit	EZS			1.5	LSb	10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load	9
Offset Error	EOS	-6	0.4	6	mV	VRxB:VRxA = 10, Gx = 0, no load, 10-bit: Code = 16	9
Offset Voltage Temperature Coefficient	VOSTC		5		µV/°C		9
Full-Scale Error, 10-bit	EFS			9	LSb	10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load	9
Gain Error, 10-bit	EG	-1	0.1	1	% of FSR	10-bit VRxB:VRxA = 10, G = 0, Code = 1008, VREF = VDD, no load	9
Gain Error Drift	ΔG/°C		-6		ppm/°C		9
Total Unadjusted Error, 10-bit	ET	-9		3	LSb	10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load	10
Integral Nonlinearity, 10-bit	INL	-0.25		0.25	LSb	10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load	10
Differential Nonlinearity, 10-bit	DNL	-0.25		0.25	LSb	10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load	10
-3 dB Bandwidth	BW		60		kHz	VREF = 3.00V ± 2V, VRxB:VRxA = 10, Gx = 0	11
Phase Margin	PM		58		°C	RL = ∞	11
Slew Rate	SR		0.15		V/µs	RL = 2k	11
Short-Circuit Current (op amp), to VSS	ISC_OA	6	10	14	mA	Short to VSS, DAC code = Full Scale	11
Short-Circuit Current (op amp), to VDD	ISC_OA	6	10	14	mA	Short to VDD, DAC code = Zero Scale	11
Settling Time	tSETTLING		16		µs	RL = 2 k	11
Band Gap Voltage	VBG	1.18	1.214	1.26	V	1.8V ≤ VDD ≤ 5.5V	11
Band Gap Short-Circuit Current, to VSS	ISC_BG	6	10	14	mA	Short to VSS	11
Band Gap Short-Circuit Current, to VDD	ISC_BG	6	10	14	mA	Short to VDD	11
Band Gap Voltage Temperature Coefficient	VBGTC		16		ppm/°C	1.8V ≤ VDD ≤ 5.5V	11
Current through VREF	IVREF			172.15	µA	Mathematically from RVREF(min) spec (at 5.5V)	12
Input Capacitance (VREF)	CREF		29		pF	VRxB:VRxA = 10 (Unbuffered mode)	12
Total Harmonic Distortion	THD		-76		dB	VREF = 2.048V ± 0.1V, VRxB:VRxA = 10, Gx = 0, Frequency = 1 kHz	12
Schmitt Trigger High Input Threshold (LAT/HVC, A0, A1)	VIH	0.45			V	1.8V ≤ VDD ≤ 5.5V; min is 0.45 VDD	13
Schmitt Trigger Low Input Threshold (LAT/HVC, A0, A1)	VIL			0.2	V	max is 0.2 VDD	13
Input Leakage Current (LAT/HVC, A0, A1)	IIL	-1		1	µA	VIN = VDD and VIN = VSS	13
SDA Output Low Voltage	VOL			0.4	V	VDD ≥ 2.0V, IOL = 3 mA	13
SDA/SCL Input High Voltage	VIH	0.7			V	1.8V ≤ VDD ≤ 5.5V; min is 0.7 VDD	13
SDA/SCL Input Low Voltage	VIL			0.3	V	1.8V ≤ VDD ≤ 5.5V; max is 0.3 VDD	13
SDA/SCL Input Leakage	IL	-1		1	µA	SCL = SDA = VSS or SCL = SDA = VDD	13
Power Supply Sensitivity	PSS		0.001	0.0035	%/%	Code = Mid-Scale	13
LAT Pin Pulse Width	tLAT	20			ns		16
Power-on Reset Delay, dual	tPOR2SIA			145	µs	Dual	17
SCL Pin Frequency, Standard mode	FSCL	0		100	kHz	Cb = 400 pF, 1.8V-5.5V	19
SCL Pin Frequency, Fast mode	FSCL	0		400	kHz	Cb = 400 pF, 2.7V-5.5V	19

CAD (KiCad official)

Symbol: MCP47CVB12-E
Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
3D model files: mcp47cvb12-e-etched.step / mcp47cvb12-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp47cvb12-e.step / mcp47cvb12-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (124 pp, sha256 00ea6d555e34c774, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# MCP47CVB12-E

**Microchip Tech** · Digital To Analog Converters (DACs) · DFN-10-EP(3x3)

MCP47CVB12-E from Microchip Tech, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage pin, 2.7V to 5.5V for full specifications (1.8V to 2.7V reduced), with about 0.1 µF ceramic bypass recommended close to the pin. |
| 2 | A0 | input | I2C slave address bit 0 pin (Schmitt Trigger input) that sets the lowest bit of the 7-bit slave address. |
| 3 | VREF | power_in | Analog voltage reference input (buffered or unbuffered) or output when the internal band gap is selected; disconnected when VDD is the reference. |
| 4 | VOUT0 | output | Buffered analog voltage output of DAC0, with about 1 Ω DC impedance in normal mode and 1 kΩ, 100 kΩ or open in power-down. |
| 5 | VOUT1 | output | Buffered analog voltage output of DAC1, with about 1 Ω DC impedance in normal mode and 1 kΩ, 100 kΩ or open in power-down. |
| 6 | LAT/HVC | input | Latch pin that transfers volatile wiper and configuration values to both DAC outputs when taken to VIL, and high-voltage command pin for MTP programming (7.5V, at least 6.4 mA, above 5.5V only during programming). |
| 7 | VSS | power_in | Ground reference pin for all circuitry on the device, to be connected to a low-impedance ground plane. |
| 8 | A1 | input | I2C slave address bit 1 pin (Schmitt Trigger input) that sets the second-lowest bit of the 7-bit slave address. |
| 9 | SCL | input | I2C serial clock input (Schmitt Trigger) supporting Standard 100 kHz, Fast 400 kHz and High-Speed up to 3.4 MHz modes. |
| 10 | SDA | bidirectional | I2C serial data input/output (Schmitt Trigger) with slope-controlled output driver. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DFN-10-EP(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2.7 |  | 5.5 | V | Full specifications | 6 |
| Supply Voltage (reduced) | VDD | 1.8 |  | 2.7 | V | DAC operation (reduced analog specifications) and serial interface | 6 |
| Operating Temperature | TA | -40 |  | 125 | °C | Extended | 6 |
| Voltage on VDD | VDD | -0.6 |  | 6.5 | V | with respect to VSS | 5 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0, VI > VDD, VI > VPP on HV pins | 5 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VDD | 5 |
| Max current out of VSS pin |  |  |  | 100 | mA | Dual | 5 |
| Max current into VDD pin |  |  |  | 100 | mA | Dual | 5 |
| Max current sourced by VOUT pin |  |  |  | 20 | mA |  | 5 |
| Max current sunk by VOUT pin |  |  |  | 20 | mA |  | 5 |
| Total power dissipation |  |  |  | 400 | mW |  | 5 |
| Storage temperature |  | -65 |  | 150 | °C |  | 5 |
| Ambient temperature with power applied |  | -55 |  | 125 | °C |  | 5 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C |  | 5 |
| Soldering temperature of leads |  |  |  | 300 | °C | 10 seconds | 5 |
| ESD HBM |  |  |  | 6 | kV | all pins | 5 |
| Power-on Reset VDD (rising) | VPOR |  |  | 1.75 | V | VDD voltages greater than the VPOR limit ensure that the device is out of Reset | 6 |
| Brown-out Reset VDD (falling) | VBOR |  |  | 1.61 | V | RAM retention voltage: (VRAM)<VBOR | 6 |
| Power-on Reset to Output-Driven Delay | TPOR2OD |  |  | 145 | µs | VDD rising, VDD >VPOR, dual output | 6 |
| Supply Current, dual, 100 kHz | IDD |  |  | 330 | µA | Dual 100 kHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale | 7 |
| Supply Current, dual, 400 kHz | IDD |  |  | 410 | µA | Dual 400 kHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale | 7 |
| Supply Current, dual, 1.7 MHz | IDD |  |  | 560 | µA | Dual 1.7 MHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale | 7 |
| Supply Current, dual, 3.4 MHz | IDD |  |  | 720 | µA | Dual 3.4 MHz, serial interface active, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale | 7 |
| Supply Current, dual, interface inactive | IDD |  |  | 280 | µA | Dual, serial interface inactive, VRxB:VRxA = 10, VOUT unloaded, VREF = VDD = 5.5V, mid-scale | 7 |
| Power-Down Current | IDDP |  | 0.65 | 3.8 | µA | PDxB:PDxA = 01, VRxB:VRxA = 10, VOUT not connected | 7 |
| Resistor Ladder Resistance | RL | 63.9 | 71 | 78.1 | kΩ | VRxB:VRxA = 10, VREF = VDD | 8 |
| Nominal VOUT Match |  |  | 0.016 | 0.3 | % | 1.8V ≤ VDD ≤ 5.5V | 8 |
| VOUT Tempco | ΔVOUT/ΔT |  | 3 |  | ppm/°C | Code = Mid-Scale, VRxB:VRxA = 00, 10 and 11 | 8 |
| Zero-Scale Error, 10-bit | EZS |  |  | 1.5 | LSb | 10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load | 9 |
| Offset Error | EOS | -6 | 0.4 | 6 | mV | VRxB:VRxA = 10, Gx = 0, no load, 10-bit: Code = 16 | 9 |
| Offset Voltage Temperature Coefficient | VOSTC |  | 5 |  | µV/°C |  | 9 |
| Full-Scale Error, 10-bit | EFS |  |  | 9 | LSb | 10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load | 9 |
| Gain Error, 10-bit | EG | -1 | 0.1 | 1 | % of FSR | 10-bit VRxB:VRxA = 10, G = 0, Code = 1008, VREF = VDD, no load | 9 |
| Gain Error Drift | ΔG/°C |  | -6 |  | ppm/°C |  | 9 |
| Total Unadjusted Error, 10-bit | ET | -9 |  | 3 | LSb | 10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load | 10 |
| Integral Nonlinearity, 10-bit | INL | -0.25 |  | 0.25 | LSb | 10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load | 10 |
| Differential Nonlinearity, 10-bit | DNL | -0.25 |  | 0.25 | LSb | 10-bit VRxB:VRxA = 10, G = 0, VREF = VDD, no load | 10 |
| -3 dB Bandwidth | BW |  | 60 |  | kHz | VREF = 3.00V ± 2V, VRxB:VRxA = 10, Gx = 0 | 11 |
| Phase Margin | PM |  | 58 |  | °C | RL = ∞ | 11 |
| Slew Rate | SR |  | 0.15 |  | V/µs | RL = 2k | 11 |
| Short-Circuit Current (op amp), to VSS | ISC_OA | 6 | 10 | 14 | mA | Short to VSS, DAC code = Full Scale | 11 |
| Short-Circuit Current (op amp), to VDD | ISC_OA | 6 | 10 | 14 | mA | Short to VDD, DAC code = Zero Scale | 11 |
| Settling Time | tSETTLING |  | 16 |  | µs | RL = 2 k | 11 |
| Band Gap Voltage | VBG | 1.18 | 1.214 | 1.26 | V | 1.8V ≤ VDD ≤ 5.5V | 11 |
| Band Gap Short-Circuit Current, to VSS | ISC_BG | 6 | 10 | 14 | mA | Short to VSS | 11 |
| Band Gap Short-Circuit Current, to VDD | ISC_BG | 6 | 10 | 14 | mA | Short to VDD | 11 |
| Band Gap Voltage Temperature Coefficient | VBGTC |  | 16 |  | ppm/°C | 1.8V ≤ VDD ≤ 5.5V | 11 |
| Current through VREF | IVREF |  |  | 172.15 | µA | Mathematically from RVREF(min) spec (at 5.5V) | 12 |
| Input Capacitance (VREF) | CREF |  | 29 |  | pF | VRxB:VRxA = 10 (Unbuffered mode) | 12 |
| Total Harmonic Distortion | THD |  | -76 |  | dB | VREF = 2.048V ± 0.1V, VRxB:VRxA = 10, Gx = 0, Frequency = 1 kHz | 12 |
| Schmitt Trigger High Input Threshold (LAT/HVC, A0, A1) | VIH | 0.45 |  |  | V | 1.8V ≤ VDD ≤ 5.5V; min is 0.45 VDD | 13 |
| Schmitt Trigger Low Input Threshold (LAT/HVC, A0, A1) | VIL |  |  | 0.2 | V | max is 0.2 VDD | 13 |
| Input Leakage Current (LAT/HVC, A0, A1) | IIL | -1 |  | 1 | µA | VIN = VDD and VIN = VSS | 13 |
| SDA Output Low Voltage | VOL |  |  | 0.4 | V | VDD ≥ 2.0V, IOL = 3 mA | 13 |
| SDA/SCL Input High Voltage | VIH | 0.7 |  |  | V | 1.8V ≤ VDD ≤ 5.5V; min is 0.7 VDD | 13 |
| SDA/SCL Input Low Voltage | VIL |  |  | 0.3 | V | 1.8V ≤ VDD ≤ 5.5V; max is 0.3 VDD | 13 |
| SDA/SCL Input Leakage | IL | -1 |  | 1 | µA | SCL = SDA = VSS or SCL = SDA = VDD | 13 |
| Power Supply Sensitivity | PSS |  | 0.001 | 0.0035 | %/% | Code = Mid-Scale | 13 |
| LAT Pin Pulse Width | tLAT | 20 |  |  | ns |  | 16 |
| Power-on Reset Delay, dual | tPOR2SIA |  |  | 145 | µs | Dual | 17 |
| SCL Pin Frequency, Standard mode | FSCL | 0 |  | 100 | kHz | Cb = 400 pF, 1.8V-5.5V | 19 |
| SCL Pin Frequency, Fast mode | FSCL | 0 |  | 400 | kHz | Cb = 400 pF, 2.7V-5.5V | 19 |

## CAD (KiCad official)

- Symbol: `MCP47CVB12-E`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `mcp47cvb12-e-etched.step` / `mcp47cvb12-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp47cvb12-e.step` / `mcp47cvb12-e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp47cvb12-e-datasheet.pdf) (124 pp, sha256 `00ea6d555e34c774`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp47cvb12-e-datasheet.pdf)

MCP47CVB12-E

Verified MCP47CVB12-E

Verification log 1 record

MCP47CVB12-E

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance