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MCP3912A1-E

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Microchip Tech Analog To Digital Converters (ADCs), QFN-28(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP3912A1-E

Microchip Tech · Analog To Digital Converters (ADCs) · QFN-28(5x5)

MCP3912A1-E from Microchip Tech, in a QFN-28(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CH1- input Inverting analog input for channel 1; max absolute voltage vs AGND is ±1V with no distortion and ±2V with no breakdown.
2 CH1+ input Noninverting analog input for channel 1; linear range is ±600 mV/GAIN with VREF = 1.2V.
3 CH2+ input Noninverting analog input for channel 2; linear range is ±600 mV/GAIN with VREF = 1.2V.
4 CH2- input Inverting analog input for channel 2; max absolute voltage vs AGND is ±1V with no distortion and ±2V with no breakdown.
5 CH3- input Inverting analog input for channel 3; max absolute voltage vs AGND is ±1V with no distortion and ±2V with no breakdown.
6 CH3+ input Noninverting analog input for channel 3; linear range is ±600 mV/GAIN with VREF = 1.2V.
7 NC unconnected No connect; for better EMI results, connect to AGND.
8 REFIN+/OUT bidirectional Noninverting voltage reference input and internal reference output; internal reference has minimal drive capability and needs buffering and a 0.1 µF ceramic bypass if used as a source.
9 REFIN- input Inverting voltage reference input; connect directly to AGND when using the internal or a single-ended reference.
10 AGND power_in Analog ground, return path for internal analog circuitry; star-connect with pin 26 and to the same node as DGND.
11 AVDD power_in Analog power supply, 2.7V to 3.6V; connect with pin 25 and bypass with 10 µF in parallel with 0.1 µF ceramic.
12 DVDD power_in Digital power supply pin, 2.7V to 3.6V.
13 DGND power_in Digital ground, return path for internal digital circuitry; star-connect with pins 15 and 23 and to the same node as AGND.
14 DR output Data ready output giving an active-low pulse of half a DMCLK period when new ADC data are available; high-impedance or logic high when inactive per DR_HIZ.
15 DGND power_in Digital ground, return path for internal digital circuitry; star-connect with pins 13 and 23.
16 OSC1/CLKI input Oscillator crystal connection or external clock input.
17 OSC2 passive Oscillator crystal connection pin.
18 CS input Serial interface chip select input; falling edge starts and rising edge ends an SPI communication, SDO is high-impedance when CS is high.
19 SCK input Serial interface clock input for SPI Mode 0,0 and 1,1, up to 20 MHz.
20 SDO tri_state Serial interface data output clocked out on the falling edge of SCK; high-impedance when CS is high.
21 SDI input Serial interface data input latched on the rising edge of SCK.
22 RESET input Master reset logic input acting as a hard reset to the default power-up configuration.
23 DGND power_in Digital ground, return path for internal digital circuitry; star-connect with pins 13 and 15.
24 DVDD power_in Digital power supply pin, 2.7V to 3.6V.
25 AVDD power_in Analog power supply, 2.7V to 3.6V; connect with pin 11 and bypass with 10 µF in parallel with 0.1 µF ceramic.
26 AGND power_in Analog ground, return path for internal analog circuitry; star-connect with pin 10 and to the same node as DGND.
27 CH0+ input Noninverting analog input for channel 0; linear range is ±600 mV/GAIN with VREF = 1.2V.
28 CH0- input Inverting analog input for channel 0; max absolute voltage vs AGND is ±1V with no distortion and ±2V with no breakdown.
29 EP passive Exposed thermal pad; must be connected to AGND or floating.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-28(5x5)
Category ADC/DAC/Data Conversion
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD (absolute maximum) VDD -0.3 4 V 3
Digital inputs and outputs w.r.t. AGND -0.3 4 V 3
Analog input w.r.t. AGND -2 2 V 3
Storage temperature -65 150 °C 3
Ambient temp. with power applied -65 125 °C 3
Soldering temperature of leads 300 °C 10 seconds 3
VREF input w.r.t. AGND (min only; max is VDD + 0.6 V) -0.6 V 3
Resolution (No Missing Codes) 24 bits OSR = 256 or greater 3
Sampling Frequency fS(DMCLK) 1 4 MHz For maximum condition, BOOST[1:0] = 11 3
Output Data Rate fD(DRCLK) 4 125 ksps For maximum condition, BOOST[1:0] = 11, OSR = 32 3
Analog Input Absolute Voltage on CHn+/- Pins CHn+/- -1 1 V All analog input channels measured to AGND 3
Offset Error VOS -2 0.2 2 mV Note 5 3
Gain Error GE -6 6 % Note 5 3
Differential Input Impedance ZIN 232 kΩ G = 1, proportional to 1/AMCLK 4
Differential Input Impedance ZIN 142 kΩ G = 2, proportional to 1/AMCLK 4
Differential Input Impedance ZIN 72 kΩ G = 4, proportional to 1/AMCLK 4
Differential Input Impedance ZIN 38 kΩ G = 8, proportional to 1/AMCLK 4
Differential Input Impedance ZIN 36 kΩ G = 16, proportional to 1/AMCLK 4
Differential Input Impedance ZIN 33 kΩ G = 32, proportional to 1/AMCLK 4
Signal-to-Noise and Distortion Ratio SINAD 92 93.5 dB Note 1 4
Total Harmonic Distortion THD -107 -103 dBc Includes the first 35 harmonics (Note 1) 4
Signal-to-Noise Ratio SNR 92 94 dB Note 1 4
Internal Voltage Reference Tolerance VREF 1.176 1.2 1.224 V VREFEXT = 0, TA = +25°C only 5
Differential Input Voltage Range (VREF+, VREF-) VREF 1.1 1.3 V VREFEXT = 1 5
Absolute Voltage REFIN- Pin VREF- -0.1 0.1 V REFIN- should be connected to AGND when VREFEXT = 0 5
Voltage Reference Input Capacitance 10 pF 5
Master Clock Input Frequency Range fMCLK 20 MHz CLKEXT = 1 (Note 7) 5
Crystal Oscillator Operating Frequency Range fXTAL 1 20 MHz CLKEXT = 0 (Note 7) 5
Analog Master Clock AMCLK 16 MHz (Note 7) 5
Operating Voltage, Analog AVDD 2.7 3.6 V 5
Operating Voltage, Digital DVDD 2.7 3.6 V 5
Operating Current, Analog IDD,A 2.8 4 mA BOOST[1:0] = 00 (Note 2) 5
Operating Current, Analog IDD,A 3.4 4.5 mA BOOST[1:0] = 01 (Note 2) 5
Operating Current, Analog IDD,A 4.7 6.4 mA BOOST[1:0] = 10 (Note 2) 5
Operating Current, Analog IDD,A 8.1 11.8 mA BOOST[1:0] = 11 (Note 2) 5
Operating Current, Digital IDD,D 0.28 0.6 mA MCLK = 4 MHz, proportional to MCLK (Note 2) 6
Shutdown Current, Analog IDDS,A 0.01 2 µA AVDD pin only (Notes 3 and 8) 6
Shutdown Current, Digital IDDS,D 0.01 4 µA DVDD pin only (Notes 3 and 8) 6
Input Leakage Current ILI -1 1 µA CS = DVDD, VIN = DGND to DVDD 6
Output Leakage Current ILO -1 1 µA CS = DVDD, VOUT = DGND or DVDD 6
Internal Capacitance (All Inputs and Outputs) CINT 7 pF TA = +25°C, SCK = 1.0 MHz, DVDD =3.3V (Note 1) 6
Serial Clock Frequency fSCK 20 MHz 7
CS Setup Time tCSS 25 ns 7
CS Hold Time tCSH 50 ns 7
CS Disable Time tCSD 50 ns 7
Data Setup Time tSU 5 ns 7
Data Hold Time tHD 10 ns 7
Serial Clock High Time tHI 20 ns 7
Serial Clock Low Time tLO 20 ns 7
Serial Clock Delay Time tCLD 50 ns 7
Serial Clock Enable Time tCLE 50 ns 7
Output Valid from SCK Low tDO 25 ns 7
Output Hold Time tHO 0 ns Note 1 7
Output Disable Time tDIS 25 ns Note 1 7
Reset Pulse Width (RESET) tMCLR 100 ns 7
Data Transfer Time to DR (Data Ready) tDODR 25 ns Note 2 7
Operating Temperature Range TA -40 125 °C Note 1 7
Thermal Resistance, 28-Lead QFN θJA 41 °C/W 7
Temperature Coefficient of internal voltage reference TCVREF 9 ppm/°C TA = -40°C to +125°C, VREFEXT = 0, VREFCAL[7:0] = 0x50 5
Measurement Error ME 0.1 % Measured with a 10,000:1 dynamic range (from 600 mVPeak to 60 µVPeak), AVDD = DVDD = 3V 4

CAD (KiCad official)

  • Symbol: MCP3912A1-E
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: QFN-28(5x5) (KiCad packages3D, STEP)
  • 3D model files: mcp3912a1-e-etched.step / mcp3912a1-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp3912a1-e.step / mcp3912a1-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (84 pp, sha256 ccb784a37702432f, retrieved 2026-10-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF