MCP3302-BI from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CH0	input	Analog input channel 0 with absolute voltage range of VSS - 0.3V to VDD + 0.3V.
2	CH1	input	Analog input channel 1 with absolute voltage range of VSS - 0.3V to VDD + 0.3V.
3	CH2	input	Analog input channel 2 with absolute voltage range of VSS - 0.3V to VDD + 0.3V.
4	CH3	input	Analog input channel 3 with absolute voltage range of VSS - 0.3V to VDD + 0.3V; differential input magnitude cannot exceed VREF - 1 LSB.
5	NC	unconnected	No connection.
6	NC	unconnected	No connection.
7	DGND	power_in	Digital ground to internal digital circuitry; must be connected to the same ground as AGND.
8	CS/SHDN	input	Chip select/shutdown input: pulled low initiates communication, pulled high ends a conversion and enters low-power standby, and must be pulled high between conversions.
9	DIN	input	SPI serial data input used to clock in input channel configuration data, latched on the rising edge of the clock.
10	DOUT	output	SPI serial data output that shifts out the A/D conversion result, changing on the falling edge of each clock.
11	CLK	input	SPI serial clock that initiates a conversion and clocks out each bit of the conversion result.
12	AGND	power_in	Analog ground to internal analog circuitry; must be connected to the same ground as DGND.
13	VREF	power_in	Reference voltage input that sets the maximum analog input range and LSB size (LSB = 2 x VREF / 8192).
14	VDD	power_in	+4.5V to 5.5V power supply for specified conversion performance, with a 0.1 µF ceramic bypass capacitor placed close to the pin.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	TSSOP-14
Category	ADC/DAC/Data Conversion
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (absolute max)	VDD			7	V		3
Storage temperature		-65		150	°C		3
Ambient temp. with power applied		-65		125	°C		3
Maximum junction temperature				150	°C		3
ESD protection on all pins (HBM)		4			kV	HBM	3
Operating voltage	VDD	4.5		5.5	V	Note 9	5
Maximum sampling frequency	FSAMPLE			100	ksps	See FCLK specification. Note 8	3
Integral nonlinearity	INL	-1	0.5	1	LSB	MCP3302/04-B; typ printed ±0.5	3
Differential nonlinearity	DNL	-1	0.5	1	LSB	Monotonic over temperature; typ printed ±0.5	3
Positive gain error		-3	-0.75	2	LSB		3
Negative gain error		-3	-0.5	2	LSB		3
Offset error		-3	3	6	LSB		3
Reference input voltage range		0.4		5.5	V	Note 2; max printed as VDD	3
Reference current drain			100	150	µA		3
Reference current drain (CS high)			0.001	3	µA	CS = VDD = 5V	3
Analog input leakage current		-1	0.001	1	µA		4
High level output voltage	VOH	4.1			V	IOH = -1 mA, VDD = 4.5V	4
Low level output voltage	VOL			0.4	V	IOL = 1 mA, VDD = 4.5V	4
Input leakage current	ILI	-10		10	µA	VIN = VSS or VDD	4
Output leakage current	ILO	-10		10	µA	VOUT = VSS or VDD	4
Pin capacitance	CIN, COUT			10	pF	TA = +25°C, F = 1 MHz, Note 1	4
Operating current	IDD		300	450	µA	VDD, VREF = 5V, DOUT unloaded	5
Standby current	IDDS		0.05	1	µA	CS = VDD = 5.0V	5
Clock frequency	FCLK	0.105		2.1	MHz	VDD = 5V, FSAMPLE = 100 ksps	4
Clock high time	THI	210			ns	Note 5	4
Clock low time	TLO	210			ns	Note 5	4
CS fall to first rising CLK edge	TSUCS	100			ns		4
Data in setup time	TSU	50			ns		4
Data in hold time	THD	50			ns		4
CLK fall to output data valid	TDO			125	ns	VDD = 5V, see Figure 1-2	4
CLK fall to output enable	TEN			125	ns	VDD = 5V, see Figure 1-2	4
CS rise to output disable	TDIS			100	ns	See test circuits, Figure 1-2 Note 1	4
CS disable time	TCSH	475			ns		4
DOUT rise time	TR			100	ns	See test circuits, Figure 1-2 Note 1	4
DOUT fall time	TF			100	ns	See test circuits, Figure 1-2 Note 1	4
Specified temperature range	TA	-40		125	°C		5
Operating temperature range	TA	-40		125	°C		5
Storage temperature range	TA	-65		150	°C		5
Thermal resistance, 14L-TSSOP	θJA		100		°C/W		5
Total harmonic distortion	THD		-91		dB	Note 3	3
Signal-to-noise and distortion	SINAD		78		dB	Note 3	3
Spurious free dynamic range	SFDR		92		dB	Note 3	3
Common mode rejection	CMRR		79		dB	Note 6	3
Power supply rejection	PSR		74		dB	Note 4	3
Switch resistance	RS		1		kΩ	See Figure 5-3	4
Sample capacitor	CSAMPLE		25		pF	See Figure 5-3	4

CAD (KiCad official)

Symbol: MCP3302-BI
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: mcp3302-bi-etched.step / mcp3302-bi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp3302-bi.step / mcp3302-bi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (48 pp, sha256 bd5671e61167c4eb, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MCP3302-BI

Verified MCP3302-BI

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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