MCP1725-ADJE

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  "title": "MCP1725-ADJE",
  "brief": "Microchip Tech Linear Voltage Regulators (LDO), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "mpn": "MCP1725-ADJE",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Power Management ICs",
    "subcategory": "Linear Voltage Regulators (LDO)",
    "datasheet": "https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/22026b.pdf",
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    "pins": [
      {
        "number": "1",
        "name": "VIN",
        "type": "power_in",
        "description": "Input voltage supply, with an operating range of 2.3V to 6.0V; an input capacitor of 1 µF to 10 µF is recommended for most applications."
      },
      {
        "number": "2",
        "name": "VIN",
        "type": "power_in",
        "description": "Input voltage supply, with an operating range of 2.3V to 6.0V; an input capacitor of 1 µF to 10 µF is recommended for most applications."
      },
      {
        "number": "3",
        "name": "SHDN",
        "type": "input",
        "description": "Active-low shutdown control: a logic-high enables the LDO output and a logic-low disables it, which also drives PWRGD low and puts the LDO in a shutdown state with about 0.1 µA typical quiescent current."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground connection to a quiet circuit ground, carrying only the LDO quiescent current (typically 120 µA)."
      },
      {
        "number": "5",
        "name": "PWRGD",
        "type": "output",
        "description": "Open-drain power good output that indicates when VOUT is within 92% (typical) of its nominal regulation value, with 2% typical hysteresis."
      },
      {
        "number": "6",
        "name": "CDELAY",
        "type": "input",
        "description": "Power good delay set-point input; an external capacitor from CDELAY to ground sets the PWRGD power-up delay from 200 µs (no capacitance) to 300 ms (0.1 µF)."
      },
      {
        "number": "7",
        "name": "ADJ",
        "type": "input",
        "description": "Voltage sense/adjust input for the adjustable version, where a resistor divider from VOUT sets the output anywhere within 0.8V to 5.0V."
      },
      {
        "number": "8",
        "name": "VOUT",
        "type": "power_out",
        "description": "Regulated output voltage of the LDO, rated up to 500 mA, which requires a minimum output capacitance of 1.0 µF for stability."
      }
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      "Package": "SOIC-8",
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        {
          "name": "Adjust Temperature Coefficient",
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          "conditions": "RPULLUP = 10 kΩ, ICDELAY = 140 nA (Typ), CDELAY = OPEN",
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          "name": "PWRGD Time Delay (rising edge), CDELAY = 0.01 µF",
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          "name": "PWRGD Time Delay (rising edge), CDELAY = 0.1 µF",
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          "name": "Detect Threshold to PWRGD Active Time Delay",
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          "max": null,
          "conditions": "VADJ or VSENSE = VPWRGD_TH + 20 mV to VPWRGD_TH - 20 mV",
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          "name": "Shutdown Logic High Input",
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          "name": "Shutdown Logic Low Input",
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          "name": "SHDN Input Leakage Current",
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          "name": "Output Delay From SHDN",
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        {
          "name": "Output Noise",
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          "unit": "µV/√Hz",
          "min": null,
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          "conditions": "IOUT = 200 mA, f = 1 kHz, COUT = 10 µF (X7R Ceramic), VOUT = 2.5V",
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        {
          "name": "Power Supply Ripple Rejection Ratio",
          "symbol": "PSRR",
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