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MCP1725-ADJE

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Microchip Tech Linear Voltage Regulators (LDO), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP1725-ADJE

Microchip Tech · Linear Voltage Regulators (LDO) · SOIC-8

MCP1725-ADJE from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input voltage supply, with an operating range of 2.3V to 6.0V; an input capacitor of 1 µF to 10 µF is recommended for most applications.
2 VIN power_in Input voltage supply, with an operating range of 2.3V to 6.0V; an input capacitor of 1 µF to 10 µF is recommended for most applications.
3 SHDN input Active-low shutdown control: a logic-high enables the LDO output and a logic-low disables it, which also drives PWRGD low and puts the LDO in a shutdown state with about 0.1 µA typical quiescent current.
4 GND power_in Ground connection to a quiet circuit ground, carrying only the LDO quiescent current (typically 120 µA).
5 PWRGD output Open-drain power good output that indicates when VOUT is within 92% (typical) of its nominal regulation value, with 2% typical hysteresis.
6 CDELAY input Power good delay set-point input; an external capacitor from CDELAY to ground sets the PWRGD power-up delay from 200 µs (no capacitance) to 300 ms (0.1 µF).
7 ADJ input Voltage sense/adjust input for the adjustable version, where a resistor divider from VOUT sets the output anywhere within 0.8V to 5.0V.
8 VOUT power_out Regulated output voltage of the LDO, rated up to 500 mA, which requires a minimum output capacitance of 1.0 µF for stability.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Operating Voltage VIN 2.3 6 V Note 1 5
Maximum Output Current IOUT 500 mA VIN = 2.3V to 6.0V, VR = 0.8V to 5.0V, Note 1 5
Input Quiescent Current IQ 120 220 µA IL = 0 mA, VIN = Note 1, VOUT = 0.8V to 5.0V 5
Input Quiescent Current for SHDN Mode ISHDN 0.1 3 µA SHDN = GND 5
Line Regulation ΔVOUT/(VOUT x ΔVIN) -0.16 0.05 0.16 %/V (Note 1) ≤ VIN ≤ 6V 5
Load Regulation ΔVOUT/VOUT -1 0.5 1 % IOUT = 1 mA to 500 mA, (Note 4) 5
Output Short Circuit Current IOUT_SC 1.2 A RLOAD < 0.1Ω, Peak Current 5
Adjust Pin Reference Voltage VADJ 0.402 0.41 0.418 V VIN = 2.3V to VIN = 6.0V, IOUT = 1 mA 5
Adjust Pin Leakage Current IADJ -10 0.01 10 nA VIN = 6.0V, VADJ = 0V to 6V 5
Adjust Temperature Coefficient TCVOUT 40 ppm/°C Note 3 5
Dropout Voltage VIN-VOUT 210 350 mV IOUT = 500 mA, (Note 5), VIN(MIN) = 2.3V 6
PWRGD Input Voltage Operating Range (TA = +25°C) VPWRGD_VIN 1 6 V TA = +25°C 6
PWRGD Input Voltage Operating Range (TA = -40°C to +125°C) VPWRGD_VIN 1.2 6 V TA = -40°C to +125°C 6
PWRGD Threshold Voltage (Referenced to VOUT), Adj VPWRGD_TH 89 92 95 %VOUT Falling Edge; VOUT < 2.5V Fixed, VOUT = Adj 6
PWRGD Threshold Hysteresis VPWRGD_HYS 1 2 3 %VOUT 6
PWRGD Output Voltage Low VPWRGD_L 0.2 0.4 V IPWRGD SINK = 1.2 mA, ADJ = 0V, SENSE = 0V 6
PWRGD Leakage PWRGD_LK 1 nA VPWRGD = VIN = 6.0V 6
PWRGD Time Delay (rising edge), CDELAY open TPG 200 µs RPULLUP = 10 kΩ, ICDELAY = 140 nA (Typ), CDELAY = OPEN 6
PWRGD Time Delay (rising edge), CDELAY = 0.01 µF TPG 10 30 55 ms CDELAY = 0.01 µF 6
PWRGD Time Delay (rising edge), CDELAY = 0.1 µF TPG 300 ms CDELAY = 0.1 µF 6
Detect Threshold to PWRGD Active Time Delay TVDET-PWRGD 200 µs VADJ or VSENSE = VPWRGD_TH + 20 mV to VPWRGD_TH - 20 mV 6
Shutdown Logic High Input VSHDN-HIGH 45 %VIN VIN = 2.3V to 6.0V 6
Shutdown Logic Low Input VSHDN-LOW 15 %VIN VIN = 2.3V to 6.0V 6
SHDN Input Leakage Current SHDNILK -0.1 0.001 0.1 µA VIN = 6V, SHDN = VIN, SHDN = GND 6
Output Delay From SHDN TOR 100 µs SHDN = GND to VIN, VOUT = GND to 95% VR 7
Output Noise eN 2 µV/√Hz IOUT = 200 mA, f = 1 kHz, COUT = 10 µF (X7R Ceramic), VOUT = 2.5V 7
Power Supply Ripple Rejection Ratio PSRR 60 dB f = 100 Hz, COUT = 10 µF, IOUT = 10 mA, VINAC = 30 mV pk-pk, CIN = 0 µF 7
Thermal Shutdown Temperature TSD 150 °C IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V 7
Thermal Shutdown Hysteresis ΔTSD 10 °C IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V 7
Operating Junction Temperature Range TJ -40 125 °C Steady State 7
Maximum Junction Temperature TJ 150 °C Transient 7
Storage Temperature Range TA -65 150 °C 7
ESD Protection on All Pins (HBM) 2 kV HBM/MM 5
ESD Protection on All Pins (MM) 200 V HBM/MM 5
Thermal Resistance, 8LD SOIC, Junction to Ambient θJA 163 °C/W 4-Layer JC51-7 Standard Board 7
Thermal Resistance, 8LD SOIC, Junction to Case θJC 38.8 °C/W 4-Layer JC51-7 Standard Board 7
Thermal Resistance, 8LD 2x3 DFN, Junction to Ambient θJA 76 °C/W 4-Layer JC51-7 Standard Board with vias 7
Thermal Resistance, 8LD 2x3 DFN, Junction to Case θJC 26 °C/W 4-Layer JC51-7 Standard Board with vias 7
Feedback Resistor R2 Allowable Range R2 10 200 kΩ Adjustable version, Section 4.1 16
Output Capacitance Minimum COUT 1 µF Section 4.3, for LDO stability 16
Output Capacitance Maximum Recommended COUT 22 µF Section 4.3, recommended maximum 16

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Package Type: MC = Plastic Dual Flat No Lead (DFN) (2x3 Body), 8-lead SN = Plastic Small Outline (150 mil Body), 8-lead 29

CAD (KiCad official)

  • Symbol: MCP1725-ADJE
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mcp1725-adje-etched.step / mcp1725-adje-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp1725-adje.step / mcp1725-adje.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (32 pp, sha256 280bae2ee8a97ab3, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF