component
MCP1725-3302E
Public Made by Adomby adom
Microchip Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MCP1725-3302E
Microchip Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
MCP1725-3302E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage supply; the datasheet gives an input operating range of 2.3V to 6.0V and recommends an input capacitor of 1 µF to 10 µF when the source is remote or a battery. |
| 2 | VIN | power_in | Second input voltage supply pin, listed in the pin table as Input Voltage Supply with the same 2.3V to 6.0V operating input range. |
| 3 | SHDN | input | Active-low shutdown control: a logic-high enables the LDO output and a logic-low disables it, which also drives PWRGD low and puts the LDO into a typical 0.1 µA quiescent shutdown state. |
| 4 | GND | power_in | Ground connection to a quiet circuit ground, which only carries the LDO quiescent current (typically 120 µA) and should return to the output capacitor return for noisy or switching inputs. |
| 5 | PWRGD | output | Open-drain power good output that indicates the LDO output is within 92% (typical) of its nominal regulation value, with about 2% typical hysteresis, and is delayed on power-up by the CDELAY setting (200 µs typical with no CDELAY capacitor). |
| 6 | CDELAY | input | Power good delay set-point input where an external capacitor to ground sets the PWRGD power-up delay from 200 µs (no capacitance) to 300 ms (0.1 µF). |
| 7 | Sense | input | Output voltage feedback input for the fixed-voltage version that compensates for voltage drops from packaging and board layout to improve load regulation. |
| 8 | VOUT | power_out | Regulated output voltage of the LDO, which requires a minimum output capacitance of 1.0 µF for stability (ceramic, tantalum or aluminum-electrolytic). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Operating Voltage | VIN | 2.3 | 6 | V | Note 1 | 5 | |
| Maximum Output Current | IOUT | 500 | mA | VIN = 2.3V to 6.0V, VR = 0.8V to 5.0V, Note 1 | 5 | ||
| Input Quiescent Current | Iq | 120 | 220 | µA | IL = 0 mA, VIN = Note 1, VOUT = 0.8V to 5.0V | 5 | |
| Input Quiescent Current for SHDN Mode | ISHDN | 0.1 | 3 | µA | SHDN = GND | 5 | |
| Line Regulation | ΔVOUT/(VOUT x ΔVIN) | -0.16 | 0.05 | 0.16 | %/V | (Note 1) ≤ VIN ≤ 6V | 5 |
| Load Regulation | ΔVOUT/VOUT | -1 | 0.5 | 1 | % | IOUT = 1 mA to 500 mA, (Note 4) | 5 |
| Output Short Circuit Current | IOUT_SC | 1.2 | A | RLOAD < 0.1Ω, Peak Current | 5 | ||
| Fixed-Output Voltage Regulation (tolerance about VR, VR = 3.3V nominal) | VOUT | -2.5 | 2.5 | % | Fixed output; VR is nominal output voltage, Note 2 | 5 | |
| Fixed-Output Voltage Regulation typical tolerance | VOUT | 0.5 | % | VR ±0.5%, Note 2 | 5 | ||
| Dropout Voltage | VIN-VOUT | 210 | 350 | mV | IOUT = 500 mA, (Note 5) | 6 | |
| PWRGD Input Voltage Operating Range | VPWRGD_VIN | 1 | 6 | V | TA = +25°C | 6 | |
| PWRGD Input Voltage Operating Range (full temperature) | VPWRGD_VIN | 1.2 | 6 | V | TA = -40°C to +125°C | 6 | |
| PWRGD Threshold Voltage (VOUT >= 2.5V Fixed) | VPWRGD_TH | 90 | 92 | 94 | %VOUT | Falling Edge, VOUT >= 2.5V Fixed | 6 |
| PWRGD Threshold Hysteresis | VPWRGD_HYS | 1 | 2 | 3 | %VOUT | 6 | |
| PWRGD Output Voltage Low | VPWRGD_L | 0.2 | 0.4 | V | ISINK = 1.2 mA, ADJ = 0V, SENSE = 0V | 6 | |
| PWRGD Leakage | PWRGD_LK | 1 | nA | VPWRGD = VIN = 6.0V | 6 | ||
| PWRGD Time Delay (CDELAY open) | TPG | 200 | µs | Rising edge, RPULLUP = 10 kΩ, ICDELAY = 140 nA (Typ), CDELAY = OPEN | 6 | ||
| PWRGD Time Delay (CDELAY = 0.01 µF) | TPG | 10 | 30 | 55 | ms | Rising edge, RPULLUP = 10 kΩ, CDELAY = 0.01 µF | 6 |
| PWRGD Time Delay (CDELAY = 0.1 µF) | TPG | 300 | ms | Rising edge, RPULLUP = 10 kΩ, CDELAY = 0.1 µF | 6 | ||
| Detect Threshold to PWRGD Active Time Delay | TVDET-PWRGD | 200 | µs | VADJ or VSENSE = VPWRGD_TH + 20 mV to VPWRGD_TH - 20 mV | 6 | ||
| Shutdown Input Logic High | VSHDN-HIGH | 45 | %VIN | VIN = 2.3V to 6.0V | 6 | ||
| Shutdown Input Logic Low | VSHDN-LOW | 15 | %VIN | VIN = 2.3V to 6.0V | 6 | ||
| SHDN Input Leakage Current | SHDNILK | -0.1 | 0.001 | 0.1 | µA | VIN = 6V, SHDN = VIN, SHDN = GND | 6 |
| Output Delay From SHDN | TOR | 100 | µs | SHDN = GND to VIN, VOUT = GND to 95% VR | 7 | ||
| Output Noise | eN | 2 | µV/√Hz | IOUT = 200 mA, f = 1 kHz, COUT = 10 µF (X7R Ceramic), VOUT = 2.5V | 7 | ||
| Power Supply Ripple Rejection Ratio | PSRR | 60 | dB | f = 100 Hz, COUT = 10 µF, IOUT = 10 mA, VINAC = 30 mV pk-pk, CIN = 0 µF | 7 | ||
| Thermal Shutdown Temperature | TSD | 150 | °C | IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V | 7 | ||
| Thermal Shutdown Hysteresis | ΔTSD | 10 | °C | IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V | 7 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | Steady State | 7 | |
| Maximum Junction Temperature | TJ | 150 | °C | Transient | 7 | ||
| Storage Temperature Range | TA | -65 | 150 | °C | 7 | ||
| Thermal Resistance, 8LD SOIC (junction to ambient) | θJA | 163 | °C/W | 4-Layer JC51-7 Standard Board | 7 | ||
| Thermal Resistance, 8LD SOIC (junction to case) | θJC | 38.8 | °C/W | 4-Layer JC51-7 Standard Board | 7 | ||
| ESD protection, HBM | 2 | kV | HBM/MM rating as printed (≥ 2 kV) | 5 | |||
| ESD protection, MM | 200 | V | HBM/MM rating as printed (≥ 200V) | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Package Type: MC = Plastic Dual Flat No Lead (DFN) (2x3 Body), 8-lead SN = Plastic Small Outline (150 mil Body), 8-lead | 29 |
CAD (KiCad official)
- Symbol:
MCP1725-3302E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp1725-3302e-etched.step/mcp1725-3302e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp1725-3302e.step/mcp1725-3302e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (32 pp, sha256
280bae2ee8a97ab3, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).