# MCP1407-E

**Microchip Tech** · Gate Drive ICs · SOP-8

MCP1407-E from Microchip Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply input for the MOSFET driver with a 4.5V to 18V range, which must be decoupled to ground with local capacitors and connected together with pin 8. |
| 2 | INPUT | input | High-impedance TTL/CMOS-compatible non-inverting control input (MCP1407) with hysteresis, withstanding -5V to VDD+0.3V. |
| 3 | NC | unconnected | No connection. |
| 4 | GND | power_in | Ground return pin that carries high peak discharge currents and must be connected together with pin 5 with a low impedance path to the supply return. |
| 5 | GND | power_in | Ground return pin that carries high peak discharge currents and must be connected together with pin 4 with a low impedance path to the supply return. |
| 6 | OUTPUT | output | CMOS push-pull output sourcing 6A peak (VDD = 18V) with 1.5A reverse current latch-up rating, to be connected together with pin 7. |
| 7 | OUTPUT | output | CMOS push-pull output sourcing 6A peak (VDD = 18V) with 1.5A reverse current latch-up rating, to be connected together with pin 6. |
| 8 | VDD | power_in | Supply input for the MOSFET driver with a 4.5V to 18V range, which must be decoupled to ground with local capacitors and connected together with pin 1. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOP-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1 High Input Voltage | VIH | 2.4 | 1.8 |  | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 4 |
| Logic 0 Low Input Voltage | VIL |  | 1.3 | 0.8 | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 4 |
| Input Current | IIN | -10 |  | 10 | µA | 0V ≤ VIN ≤ VDD | 4 |
| Input Voltage | VIN | -5 |  |  | V | Max printed as VDD+0.3 | 4 |
| Low Output Voltage | VOL |  |  | 0.025 | V | DC Test | 4 |
| Output Resistance, High | ROH |  | 2.1 | 2.8 | Ω | IOUT = 10 mA, VDD = 18V | 4 |
| Output Resistance, Low | ROL |  | 1.5 | 2.5 | Ω | IOUT = 10 mA, VDD = 18V | 4 |
| Rise Time | tR |  | 20 | 30 | ns | CL = 2500 pF, Figure 4-1, Figure 4-2 | 4 |
| Fall Time | tF |  | 20 | 30 | ns | CL = 2500 pF, Figure 4-1, Figure 4-2 | 4 |
| Delay Time | tD1 |  | 40 | 55 | ns | Figure 4-1, Figure 4-2 | 4 |
| Supply Voltage | VDD | 4.5 |  | 18 | V |  | 4 |
| Power Supply Current | IS |  | 130 | 250 | µA | VIN = 3V | 4 |
| Power Supply Current | IS |  | 35 | 100 | µA | VIN = 0V | 4 |
| Logic 1 High Input Voltage (over temperature) | VIH | 2.4 |  |  | V | Operating temperature range, 4.5V ≤ VDD ≤ 18V | 5 |
| Logic 0 Low Input Voltage (over temperature) | VIL |  |  | 0.8 | V | Operating temperature range, 4.5V ≤ VDD ≤ 18V | 5 |
| Input Current (over temperature) | IIN | -10 |  | 10 | µA | 0V ≤ VIN ≤ VDD | 5 |
| Input Voltage (over temperature) | VIN | -5 |  |  | V | Max printed as VDD+0.3 | 5 |
| Low Output Voltage (over temperature) | VOL |  |  | 0.025 | V | DC TEST | 5 |
| Output Resistance, High (over temperature) | ROH |  | 3 | 5 | Ω | IOUT = 10 mA, VDD = 18V | 5 |
| Output Resistance, Low (over temperature) | ROL |  | 2.3 | 5 | Ω | IOUT = 10 mA, VDD = 18V | 5 |
| Rise Time (over temperature) | tR |  | 25 | 40 | ns | CL = 2500 pF, Figure 4-1, Figure 4-2 | 5 |
| Fall Time (over temperature) | tF |  | 25 | 40 | ns | CL = 2500 pF, Figure 4-1, Figure 4-2 | 5 |
| Delay Time (over temperature) | tD1 |  | 50 | 65 | ns | Figure 4-1, Figure 4-2 | 5 |
| Supply Voltage (over temperature) | VDD | 4.5 |  | 18 | V |  | 5 |
| Power Supply Current (over temperature) | IS |  | 200 | 500 | µA | VIN = 3V | 5 |
| Power Supply Current (over temperature) | IS |  | 50 | 150 | µA | VIN = 0V | 5 |
| Specified Temperature Range | TA | -40 |  | 125 | °C |  | 5 |
| Storage Temperature Range | TA | -65 |  | 150 | °C |  | 5 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C |  | 5 |
| Supply Voltage (absolute maximum) |  |  |  | 20 | V |  | 4 |
| Input Voltage (absolute maximum) |  | -5 |  |  | V | Printed as (VDD + 0.3V) to (GND, 5V) | 4 |
| Input Current (absolute maximum) |  |  |  | 50 | mA | VIN>VDD | 4 |
| Thermal Resistance, 8L-SOIC | θJA |  | 155 |  | °C/W |  | 5 |
| Peak Output Current | IPK |  | 6 |  | A | VDD ≤ 18V (Note 2) | 4 |
| Latch-Up Protection Withstand Reverse Current | IREV |  | 1.5 |  | A | Duty cycle ≤ 2%, t ≤ 300 µsec | 4 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | PA = Plastic DIP, (300 mil body), 8-lead SN = Plastic SOIC (150 mil Body), 8-Lead | 25 |

## CAD (KiCad official)

- Symbol: `MCP1407-E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `mcp1407-e-etched.step` / `mcp1407-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp1407-e.step` / `mcp1407-e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp1407-e-datasheet.pdf) (28 pp, sha256 `4621b8975c45a5cb`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp1407-e-datasheet.pdf)