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MC74VHC595DR2G

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onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74VHC595DR2G

onsemi · Shift Registers · SOIC-16

MC74VHC595DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB tri_state Parallel data output B of the 3-state storage register; forced to high impedance when OE is high.
2 QC tri_state Parallel data output C of the 3-state storage register; forced to high impedance when OE is high.
3 QD tri_state Parallel data output D of the 3-state storage register; forced to high impedance when OE is high.
4 QE tri_state Parallel data output E of the 3-state storage register; forced to high impedance when OE is high.
5 QF tri_state Parallel data output F of the 3-state storage register; forced to high impedance when OE is high.
6 QG tri_state Parallel data output G of the 3-state storage register; forced to high impedance when OE is high.
7 QH tri_state Parallel data output H of the 3-state storage register; forced to high impedance when OE is high.
8 GND power_in Ground reference pin for the device.
9 SQH output Serial data output taken from the shift register stage H, used for cascading devices.
10 SCLR input Active-low reset of the shift register; a low level clears the shift register contents, and the input tolerates up to 7 V.
11 SCK input Shift clock input; data is shifted into the shift register on its positive-going transition.
12 RCK input Register clock input; the storage register is loaded from the shift register on its positive-going transition.
13 OE input Active-low output enable; a high level forces QA to QH into the high-impedance state, while a low level enables them.
14 SI input Serial data input to the shift register; inputs tolerate voltages up to 7 V.
15 QA tri_state Parallel data output A of the 3-state storage register; forced to high impedance when OE is high.
16 VCC power_in Positive supply pin; the device is designed for a 2.0 V to 5.5 V operating range.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC 2 5.5 V 4
DC Input Voltage Vin 0 5.5 V 4
DC Output Voltage Vout 0 V 4
Operating Temperature, All Package Types TA -55 125 °C 4
Input Rise and Fall Time tr, tf 0 100 ns/V VCC = 3.3 V ±0.3 V 4
Input Rise and Fall Time tr, tf 0 20 ns/V VCC = 5.0 V ±0.5 V 4
DC Supply Voltage (maximum rating) VCC -0.5 7 V 4
DC Input Voltage (maximum rating) Vin -0.5 7 V 4
DC Output Voltage (maximum rating) Vout -0.5 V 4
Input Diode Current IIK -20 mA 4
Output Diode Current IOK -20 20 mA 4
DC Output Current, per Pin Iout -25 25 mA 4
DC Supply Current, VCC and GND Pins ICC -50 50 mA 4
Power Dissipation in Still Air, SOIC Packages PD 500 mW Still air, SOIC packages 4
Storage Temperature Tstg -65 150 °C 4
Minimum High-Level Input Voltage VIH 1.5 V VCC = 2.0 V, TA = 25°C 5
Minimum High-Level Input Voltage VIH 2.1 V VCC = 3.0 V, TA = 25°C 5
Minimum High-Level Input Voltage VIH 3.15 V VCC = 4.5 V, TA = 25°C 5
Minimum High-Level Input Voltage VIH 3.85 V VCC = 5.5 V, TA = 25°C 5
Maximum Low-Level Input Voltage VIL 0.59 V VCC = 2.0 V, TA = 25°C 5
Maximum Low-Level Input Voltage VIL 0.9 V VCC = 3.0 V, TA = 25°C 5
Maximum Low-Level Input Voltage VIL 1.35 V VCC = 4.5 V, TA = 25°C 5
Maximum Low-Level Input Voltage VIL 1.65 V VCC = 5.5 V, TA = 25°C 5
Minimum High-Level Output Voltage VOH 1.9 V VIN = VIH or VIL, IOH = −50 μA, VCC = 2.0 V, TA = 25°C 5
Minimum High-Level Output Voltage VOH 2.9 V VIN = VIH or VIL, IOH = −50 μA, VCC = 3.0 V, TA = 25°C 5
Minimum High-Level Output Voltage VOH 4.4 V VIN = VIH or VIL, IOH = −50 μA, VCC = 4.5 V, TA = 25°C 5
Minimum High-Level Output Voltage VOH 2.58 V VIN = VIH or VIL, IOH = −4 mA, VCC = 3.0 V, TA = 25°C 5
Minimum High-Level Output Voltage VOH 3.94 V VIN = VIH or VIL, IOH = −8 mA, VCC = 4.5 V, TA = 25°C 5
Minimum High-Level Output Voltage VOH 2.34 V VIN = VIH or VIL, IOH = −4 mA, VCC = 3.0 V, TA = 125°C 5
Minimum High-Level Output Voltage VOH 3.66 V VIN = VIH or VIL, IOH = −8 mA, VCC = 4.5 V, TA = 125°C 5
Maximum Low-Level Output Voltage VOL 0 0.1 V VIN = VIH or VIL, IOL = 50 μA, VCC = 2.0 V, TA = 25°C 5
Maximum Low-Level Output Voltage VOL 0.36 V VIN = VIH or VIL, IOL = 4 mA, VCC = 3.0 V, TA = 25°C 5
Maximum Low-Level Output Voltage VOL 0.52 V VIN = VIH or VIL, IOL = 4 mA, VCC = 3.0 V, TA = 125°C 5
Maximum Input Leakage Current IIN -0.1 0.1 μA VIN = 5.5 V or GND, 0 to 5.5 V, TA = 25°C 5
Maximum Input Leakage Current IIN -1 1 μA VIN = 5.5 V or GND, 0 to 5.5 V, TA = 125°C 5
Maximum Quiescent Supply Current ICC 4 μA VIN = VCC or GND, VCC = 5.5 V, TA = 25°C 5
Maximum Quiescent Supply Current ICC 40 μA VIN = VCC or GND, VCC = 5.5 V, TA = 125°C 5
Three-State Output Off-State Current IOZ -0.25 0.25 μA VIN = VIH or VIL, VOUT = VCC or GND, VCC = 5.5 V, TA = 25°C 5
Three-State Output Off-State Current IOZ -2.5 2.5 μA VIN = VIH or VIL, VOUT = VCC or GND, VCC = 5.5 V, TA = 125°C 5
Maximum Clock Frequency (50% Duty Cycle) fmax 80 150 MHz VCC = 3.3 ± 0.3 V, TA = 25°C 6
Maximum Clock Frequency (50% Duty Cycle) fmax 135 185 MHz VCC = 5.0 ± 0.5 V, TA = 25°C 6
Maximum Clock Frequency (50% Duty Cycle) fmax 70 MHz VCC = 3.3 ± 0.3 V, TA = 125°C 6
Maximum Clock Frequency (50% Duty Cycle) fmax 115 MHz VCC = 5.0 ± 0.5 V, TA = 125°C 6
Propagation Delay, SCK to SQH tPLH, tPHL 8.8 13 ns VCC = 3.3 ± 0.3 V, CL = 15 pF, TA = 25°C 6
Propagation Delay, SCK to SQH tPLH, tPHL 11.3 16.5 ns VCC = 3.3 ± 0.3 V, CL = 50 pF, TA = 25°C 6
Propagation Delay, SCK to SQH tPLH, tPHL 6.2 8.2 ns VCC = 5.0 ± 0.5 V, CL = 15 pF, TA = 25°C 6
Propagation Delay, SCK to SQH tPLH, tPHL 7.7 10.2 ns VCC = 5.0 ± 0.5 V, CL = 50 pF, TA = 25°C 6
Input Capacitance CIN 4 10 pF TA = 25°C 6
Three-State Output Capacitance (Output in High-Impedance State), QA-QH COUT 6 10 pF Output in high-impedance state, TA = 25°C 6
Quiet Output Maximum Dynamic VOL VOLP 0.8 1 V tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C 6
Quiet Output Minimum Dynamic VOL VOLV -1 -0.8 V tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C 6
Setup Time, SI to SCK tsu 3.5 ns VCC = 3.3 V, TA = −55 to 125°C 7
Setup Time, SI to SCK tsu 3 ns VCC = 5.0 V, TA = −55 to 125°C 7
Pulse Width, SCK or RCK tw 5 ns VCC = 3.3 V, TA = −55 to 125°C 7
Thermal Derating, SOIC Packages -7 mW/°C From 65 to 125°C 4

CAD (KiCad official)

  • Symbol: MC74VHC595DR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: mc74vhc595dr2g-etched.step / mc74vhc595dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74vhc595dr2g.step / mc74vhc595dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (11 pp, sha256 a7ed400791f6e932, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF