MC74VHC1G08DFT2G

{
 "schema": "adom.pads/1",
 "slug": "mc74vhc1g08dft2g",
 "footprint": "SOT-353_SC-70-5",
 "generated_from": {
  "footprint": "SOT-353_SC-70-5@sha256:869e17094994ff78",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -0.8375,
   -0.65
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-353_SC-70-5@sha256:869e17094994ff78"
 },
 "pad_count": 5,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "IN B",
   "type": "input",
   "description": "AND gate input B. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V, VIL = 1.35 V max at VCC = 4.5 V. Tolerates input voltages up to 7.0 V regardless of VCC, permitting 5 V-to-3 V level shifting.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "IN A",
   "type": "input",
   "description": "AND gate input A. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V, VIL = 1.35 V max at VCC = 4.5 V. Tolerates input voltages up to 7.0 V regardless of VCC.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference (0 V) for the device.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "OUT Y",
   "type": "output",
   "description": "AND gate output Y (Y = A AND B). Push-pull CMOS output, VOH >= 3.80 V min and VOL <= 0.44 V max at VCC = 4.5 V with +/-8 mA drive. Absolute-max output sink/source current +/-12.5 mA.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply. Recommended operating range 2.0 V to 5.5 V; absolute maximum -0.5 V to 7.0 V. Bypass to GND with a local ceramic capacitor.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}