# MC74LCX240DTR2G

**onsemi** · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

MC74LCX240DTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for outputs 1O0 to 1O3; when HIGH it disables those outputs into the high-impedance (HIGH Z) state. |
| 2 | 1D0 | input | Data input 0 for the first buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 3 | 2O0 | tri_state | Inverting 3-state output 0 of the second buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 4 | 1D1 | input | Data input 1 for the first buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 5 | 2O1 | tri_state | Inverting 3-state output 1 of the second buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 6 | 1D2 | input | Data input 2 for the first buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 7 | 2O2 | tri_state | Inverting 3-state output 2 of the second buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 8 | 1D3 | input | Data input 3 for the first buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 9 | 2O3 | tri_state | Inverting 3-state output 3 of the second buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | 2D3 | input | Data input 3 for the second buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 12 | 1O3 | tri_state | Inverting 3-state output 3 of the first buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 13 | 2D2 | input | Data input 2 for the second buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 14 | 1O2 | tri_state | Inverting 3-state output 2 of the first buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 15 | 2D1 | input | Data input 1 for the second buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 16 | 1O1 | tri_state | Inverting 3-state output 1 of the first buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 17 | 2D0 | input | Data input 0 for the second buffer bank; TTL-compatible and 5 V tolerant, with inputs rated to 5.5 V. |
| 18 | 1O0 | tri_state | Inverting 3-state output 0 of the first buffer bank, rated for 24 mA balanced sink and source at VCC = 3.0 V to 3.6 V. |
| 19 | 2OE | input | Active-low output enable for outputs 2O0 to 2O3; when HIGH it disables those outputs into the high-impedance (HIGH Z) state. |
| 20 | VCC | power_in | Supply voltage; the datasheet specifies 2.0 V to 3.6 V operating (2.3 V to 3.6 V in the description) and 1.5 V minimum for data retention only. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage, Operating | VCC | 2 | 3.3 | 3.6 | V | Operating | 3 |
| Supply Voltage, Data Retention Only | VCC | 1.5 | 3.3 | 3.6 | V | Data Retention Only | 3 |
| Input Voltage | VI | 0 |  | 5.5 | V |  | 3 |
| Output Voltage, HIGH or LOW State | VO | 0 |  |  | V | HIGH or LOW State | 3 |
| Output Voltage, 3-State | VO | 0 |  | 5.5 | V | 3-State | 3 |
| HIGH Level Output Current | IOH | -24 |  |  | mA | VCC = 3.0 V − 3.6 V | 3 |
| LOW Level Output Current | IOL |  |  | 24 | mA | VCC = 3.0 V − 3.6 V | 3 |
| HIGH Level Output Current | IOH | -12 |  |  | mA | VCC = 2.7 V − 3.0 V | 3 |
| LOW Level Output Current | IOL |  |  | 12 | mA | VCC = 2.7 V − 3.0 V | 3 |
| Operating Free-Air Temperature | TA | -40 |  | 125 | °C |  | 3 |
| Input Transition Rise or Fall Rate | t/V | 0 |  | 10 | ns/V | VIN from 0.8 V to 2.0 V, VCC = 3.0 V | 3 |
| DC Supply Voltage | VCC | -0.5 |  | 7 | V |  | 3 |
| DC Input Voltage | VI | -0.5 |  | 7 | V |  | 3 |
| DC Output Voltage | VO | -0.5 |  | 7 | V | Output in 3-State | 3 |
| DC Output Voltage | VO | -0.5 |  |  | V | Output in HIGH or LOW State (Note 1) | 3 |
| DC Input Diode Current | IIK | -50 |  |  | mA | VI < GND | 3 |
| DC Output Diode Current | IOK | -50 |  |  | mA | VO < GND | 3 |
| DC Output Diode Current | IOK |  |  | 50 | mA | VO > VCC | 3 |
| DC Output Source/Sink Current | IO | -50 |  | 50 | mA |  | 3 |
| DC Supply Current, Per Supply Pin | ICC | -100 |  | 100 | mA | Per Supply Pin | 3 |
| DC Ground Current, Per Ground Pin | IGND | -100 |  | 100 | mA | Per Ground Pin | 3 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 3 |
| HIGH Level Input Voltage | VIH | 2 |  |  | V | 2.7 V ≤ VCC ≤ 3.6 V; TA = −40°C to +125°C | 3 |
| LOW Level Input Voltage | VIL |  |  | 0.8 | V | 2.7 V ≤ VCC ≤ 3.6 V; TA = −40°C to +125°C | 3 |
| HIGH Level Output Voltage | VOH | 2.2 |  |  | V | VCC = 2.7 V; IOH = −12 mA; TA = −40°C to +125°C | 3 |
| HIGH Level Output Voltage | VOH | 2.4 |  |  | V | VCC = 3.0 V; IOH = −18 mA; TA = −40°C to +125°C | 3 |
| LOW Level Output Voltage | VOL |  |  | 0.2 | V | 2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 µA; TA = −40°C to +125°C | 4 |
| LOW Level Output Voltage | VOL |  |  | 0.4 | V | VCC = 2.7 V; IOL = 12 mA; TA = −40°C to +125°C | 4 |
| LOW Level Output Voltage | VOL |  |  | 0.6 | V | VCC = 3.0 V; IOL = 24 mA; TA = −40°C to +125°C | 4 |
| 3-State Output Current | IOZ | -5 |  | 5 | µA | VCC = 3.6 V, VIN = VIH or VIL, VOUT = 0 to 5.5 V; TA = −40°C to +125°C | 4 |
| Power Off Leakage Current | IOFF |  |  | 10 | µA | VCC = 0, VIN = 5.5 V or VOUT = 5.5 V; TA = −40°C to +125°C | 4 |
| Input Leakage Current | IIN | -5 |  | 5 | µA | VCC = 3.6 V, VIN = 5.5 V or GND; TA = −40°C to +125°C | 4 |
| Quiescent Supply Current | ICC |  |  | 10 | µA | VCC = 3.6 V, VIN = 5.5 V or GND; TA = −40°C to +125°C | 4 |
| Increase in ICC per Input | ICC |  |  | 500 | µA | 2.3 V ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V; TA = −40°C to +125°C | 4 |
| Propagation Delay Input to Output (tPLH) | tPLH | 1.5 |  | 6.5 | ns | VCC = 3.0 V to 3.6 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Propagation Delay Input to Output (tPLH) | tPLH |  |  | 7.5 | ns | VCC = 2.7 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Propagation Delay Input to Output (tPHL) | tPHL | 1.5 |  | 6.5 | ns | VCC = 3.0 V to 3.6 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Propagation Delay Input to Output (tPHL) | tPHL |  |  | 7.5 | ns | VCC = 2.7 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Enable Time to High Level | tPZH | 1.5 |  | 8 | ns | VCC = 3.0 V to 3.6 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Enable Time to High Level | tPZH |  |  | 9 | ns | VCC = 2.7 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Enable Time to Low Level | tPZL | 1.5 |  | 8 | ns | VCC = 3.0 V to 3.6 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Enable Time to Low Level | tPZL |  |  | 9 | ns | VCC = 2.7 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Disable Time From High Level | tPHZ | 1.5 |  | 7 | ns | VCC = 3.0 V to 3.6 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Disable Time From High Level | tPHZ |  |  | 8 | ns | VCC = 2.7 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Disable Time From Low Level | tPLZ | 1.5 |  | 7 | ns | VCC = 3.0 V to 3.6 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output Disable Time From Low Level | tPLZ |  |  | 8 | ns | VCC = 2.7 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output-to-Output Skew (tOSHL) | tOSHL |  |  | 1 | ns | Note 3; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Output-to-Output Skew (tOSLH) | tOSLH |  |  | 1 | ns | Note 3; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; TA = −40°C to +125°C | 4 |
| Dynamic LOW Peak Voltage | VOLP |  |  | 0.8 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25°C | 4 |
| Dynamic LOW Valley Voltage | VOLV |  |  | 0.8 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25°C | 4 |
| Input Capacitance | CIN |  | 7 |  | pF | VCC = 3.3 V, VI = 0 V or VCC | 4 |
| Output Capacitance | COUT |  | 8 |  | pF | VCC = 3.3 V, VI = 0 V or VCC | 4 |
| Power Dissipation Capacitance | CPD |  | 25 |  | pF | 10 MHz, VCC = 3.3 V, VI = 0 V or VCC | 4 |

## CAD (KiCad official)

- Symbol: `MC74LCX240DTR2G`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `mc74lcx240dtr2g-etched.step` / `mc74lcx240dtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74lcx240dtr2g.step` / `mc74lcx240dtr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74lcx240dtr2-d.pdf) (8 pp, sha256 `c24f3e24c01ab94f`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mc74lcx240dtr2g-datasheet.pdf)