component
MC74HCU04ADR2G
Public Made by Adomby adom
onsemi Inverters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74HCU04ADR2G
onsemi · Inverters · SOIC-14
MC74HCU04ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input of inverter 1; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 2 | Y1 | output | Inverted output of inverter 1; unused outputs must be left open. |
| 3 | A2 | input | Input of inverter 2; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 4 | Y2 | output | Inverted output of inverter 2; unused outputs must be left open. |
| 5 | A3 | input | Input of inverter 3; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 6 | Y3 | output | Inverted output of inverter 3; unused outputs must be left open. |
| 7 | GND | power_in | Ground reference for all voltages; the supply is specified referenced to GND. |
| 8 | Y4 | output | Inverted output of inverter 4; unused outputs must be left open. |
| 9 | A4 | input | Input of inverter 4; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 10 | Y5 | output | Inverted output of inverter 5; unused outputs must be left open. |
| 11 | A5 | input | Input of inverter 5; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 12 | Y6 | output | Inverted output of inverter 6; unused outputs must be left open. |
| 13 | A6 | input | Input of inverter 6; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 14 | VCC | power_in | Positive supply, 2.0 to 6.0 V referenced to GND per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Max is VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | All package types | 2 | |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Max is VCC+0.5 | 2 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Max is VCC+0.5 | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | 2 | ||
| DC Output Current, per Pin | Iout | -25 | 25 | mA | 2 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 2 | ||
| Power Dissipation in Still Air | PD | 500 | mW | SOIC package; derate -7 mW/°C from 65 to 125°C | 2 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature, 1 mm from case for 10 Seconds | TL | 260 | °C | SOIC or TSSOP package | 2 | ||
| Minimum High-Level Input Voltage | VIH | 1.7 | V | VCC 2.0 V; TA -55 to 125°C | 2 | ||
| Minimum High-Level Input Voltage | VIH | 2.5 | V | VCC 3.0 V; TA -55 to 125°C | 2 | ||
| Minimum High-Level Input Voltage | VIH | 3.6 | V | VCC 4.5 V; TA -55 to 125°C | 2 | ||
| Minimum High-Level Input Voltage | VIH | 4.8 | V | VCC 6.0 V; TA -55 to 125°C | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 0.3 | V | VCC 2.0 V; TA -55 to 125°C | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC 3.0 V; TA -55 to 125°C | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 0.8 | V | VCC 4.5 V; TA -55 to 125°C | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 1.1 | V | VCC 6.0 V; TA -55 to 125°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 1.8 | V | VCC 2.0 V; Vin=GND; /Iout/ ≤ 20 µA; TA -55 to 125°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 4 | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 20 µA; TA -55 to 125°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 5.5 | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 20 µA; TA -55 to 125°C | 2 | ||
| Maximum Low-Level Output Voltage | VOL | 0.2 | V | VCC 2.0 V; Vin=VCC; /Iout/ ≤ 20 µA; TA -55 to 125°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.5 | V | VCC 4.5 V; Vin=VCC; /Iout/ ≤ 20 µA; TA -55 to 125°C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 2.36 | V | VCC 3.0 V; Vin=GND; /Iout/ ≤ 2.4 mA; TA -55 to 25°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 2.26 | V | VCC 3.0 V; Vin=GND; /Iout/ ≤ 2.4 mA; TA 85°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 2.2 | V | VCC 3.0 V; Vin=GND; /Iout/ ≤ 2.4 mA; TA 125°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 3.86 | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 4.0 mA; TA -55 to 25°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 3.76 | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 4.0 mA; TA 85°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 4.0 mA; TA 125°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 5.36 | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 5.2 mA; TA -55 to 25°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 5.26 | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 5.2 mA; TA 85°C | 2 | ||
| Minimum High-Level Output Voltage | VOH | 5.2 | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 5.2 mA; TA 125°C | 2 | ||
| Maximum Low-Level Output Voltage | VOL | 0.32 | V | VCC 3.0 V; Vin=VCC; /Iout/ ≤ 2.4 mA; TA -55 to 125°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.37 | V | VCC 4.5 V; Vin=VCC; /Iout/ ≤ 4.0 mA; TA 85°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC 6.0 V; Vin=VCC; /Iout/ ≤ 5.2 mA; TA 85°C | 3 | ||
| Maximum Input Leakage Current | Iin | -0.1 | 0.1 | µA | VCC 6.0 V; Vin=VCC or GND; TA -55 to 25°C | 3 | |
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC 6.0 V; Vin=VCC or GND; TA 85°C | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 1 | µA | VCC 6.0 V; Vin=VCC or GND; Iout=0 µA; TA -55 to 25°C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 10 | µA | VCC 6.0 V; Vin=VCC or GND; Iout=0 µA; TA 85°C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | VCC 6.0 V; Vin=VCC or GND; Iout=0 µA; TA 125°C | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 | |||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 70 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA -55 to 25°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 90 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 85°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 105 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 125°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 12 | ns | VCC 6.0 V; CL=50 pF; Input tr=tf=6 ns; TA -55 to 25°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 15 | ns | VCC 6.0 V; CL=50 pF; Input tr=tf=6 ns; TA 85°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 18 | ns | VCC 6.0 V; CL=50 pF; Input tr=tf=6 ns; TA 125°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 75 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA -55 to 25°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 95 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 85°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 110 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 125°C | 3 |
CAD (KiCad official)
- Symbol:
MC74HCU04ADR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hcu04adr2g-etched.step/mc74hcu04adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hcu04adr2g.step/mc74hcu04adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (9 pp, sha256
e154ad67b07920fc, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed (audit)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HCU04ADR2G
**onsemi** · Inverters · SOIC-14
MC74HCU04ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input of inverter 1; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 2 | Y1 | output | Inverted output of inverter 1; unused outputs must be left open. |
| 3 | A2 | input | Input of inverter 2; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 4 | Y2 | output | Inverted output of inverter 2; unused outputs must be left open. |
| 5 | A3 | input | Input of inverter 3; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 6 | Y3 | output | Inverted output of inverter 3; unused outputs must be left open. |
| 7 | GND | power_in | Ground reference for all voltages; the supply is specified referenced to GND. |
| 8 | Y4 | output | Inverted output of inverter 4; unused outputs must be left open. |
| 9 | A4 | input | Input of inverter 4; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 10 | Y5 | output | Inverted output of inverter 5; unused outputs must be left open. |
| 11 | A5 | input | Input of inverter 5; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 12 | Y6 | output | Inverted output of inverter 6; unused outputs must be left open. |
| 13 | A6 | input | Input of inverter 6; unused inputs must be tied to GND or VCC and Vin must stay between GND and VCC. |
| 14 | VCC | power_in | Positive supply, 2.0 to 6.0 V referenced to GND per the recommended operating conditions. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | | 6 | V | Referenced to GND | 2 |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | | | V | Max is VCC | 2 |
| Operating Temperature, All Package Types | TA | -55 | | 125 | °C | All package types | 2 |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | | 7 | V | Referenced to GND | 2 |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | | | V | Max is VCC+0.5 | 2 |
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | | | V | Max is VCC+0.5 | 2 |
| DC Input Current, per Pin | Iin | -20 | | 20 | mA | | 2 |
| DC Output Current, per Pin | Iout | -25 | | 25 | mA | | 2 |
| DC Supply Current, VCC and GND Pins | ICC | -50 | | 50 | mA | | 2 |
| Power Dissipation in Still Air | PD | | | 500 | mW | SOIC package; derate -7 mW/°C from 65 to 125°C | 2 |
| Storage Temperature | Tstg | -65 | | 150 | °C | | 2 |
| Lead Temperature, 1 mm from case for 10 Seconds | TL | | | 260 | °C | SOIC or TSSOP package | 2 |
| Minimum High-Level Input Voltage | VIH | 1.7 | | | V | VCC 2.0 V; TA -55 to 125°C | 2 |
| Minimum High-Level Input Voltage | VIH | 2.5 | | | V | VCC 3.0 V; TA -55 to 125°C | 2 |
| Minimum High-Level Input Voltage | VIH | 3.6 | | | V | VCC 4.5 V; TA -55 to 125°C | 2 |
| Minimum High-Level Input Voltage | VIH | 4.8 | | | V | VCC 6.0 V; TA -55 to 125°C | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 0.3 | V | VCC 2.0 V; TA -55 to 125°C | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 0.5 | V | VCC 3.0 V; TA -55 to 125°C | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 0.8 | V | VCC 4.5 V; TA -55 to 125°C | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 1.1 | V | VCC 6.0 V; TA -55 to 125°C | 2 |
| Minimum High-Level Output Voltage | VOH | 1.8 | | | V | VCC 2.0 V; Vin=GND; /Iout/ ≤ 20 µA; TA -55 to 125°C | 2 |
| Minimum High-Level Output Voltage | VOH | 4 | | | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 20 µA; TA -55 to 125°C | 2 |
| Minimum High-Level Output Voltage | VOH | 5.5 | | | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 20 µA; TA -55 to 125°C | 2 |
| Maximum Low-Level Output Voltage | VOL | | | 0.2 | V | VCC 2.0 V; Vin=VCC; /Iout/ ≤ 20 µA; TA -55 to 125°C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.5 | V | VCC 4.5 V; Vin=VCC; /Iout/ ≤ 20 µA; TA -55 to 125°C | 3 |
| Minimum High-Level Output Voltage | VOH | 2.36 | | | V | VCC 3.0 V; Vin=GND; /Iout/ ≤ 2.4 mA; TA -55 to 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 2.26 | | | V | VCC 3.0 V; Vin=GND; /Iout/ ≤ 2.4 mA; TA 85°C | 2 |
| Minimum High-Level Output Voltage | VOH | 2.2 | | | V | VCC 3.0 V; Vin=GND; /Iout/ ≤ 2.4 mA; TA 125°C | 2 |
| Minimum High-Level Output Voltage | VOH | 3.86 | | | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 4.0 mA; TA -55 to 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 3.76 | | | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 4.0 mA; TA 85°C | 2 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC 4.5 V; Vin=GND; /Iout/ ≤ 4.0 mA; TA 125°C | 2 |
| Minimum High-Level Output Voltage | VOH | 5.36 | | | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 5.2 mA; TA -55 to 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 5.26 | | | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 5.2 mA; TA 85°C | 2 |
| Minimum High-Level Output Voltage | VOH | 5.2 | | | V | VCC 6.0 V; Vin=GND; /Iout/ ≤ 5.2 mA; TA 125°C | 2 |
| Maximum Low-Level Output Voltage | VOL | | | 0.32 | V | VCC 3.0 V; Vin=VCC; /Iout/ ≤ 2.4 mA; TA -55 to 125°C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.37 | V | VCC 4.5 V; Vin=VCC; /Iout/ ≤ 4.0 mA; TA 85°C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC 6.0 V; Vin=VCC; /Iout/ ≤ 5.2 mA; TA 85°C | 3 |
| Maximum Input Leakage Current | Iin | -0.1 | | 0.1 | µA | VCC 6.0 V; Vin=VCC or GND; TA -55 to 25°C | 3 |
| Maximum Input Leakage Current | Iin | -1 | | 1 | µA | VCC 6.0 V; Vin=VCC or GND; TA 85°C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 1 | µA | VCC 6.0 V; Vin=VCC or GND; Iout=0 µA; TA -55 to 25°C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 10 | µA | VCC 6.0 V; Vin=VCC or GND; Iout=0 µA; TA 85°C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 40 | µA | VCC 6.0 V; Vin=VCC or GND; Iout=0 µA; TA 125°C | 3 |
| Maximum Input Capacitance | Cin | | | 10 | pF | | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 70 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA -55 to 25°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 90 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 85°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 105 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 125°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 12 | ns | VCC 6.0 V; CL=50 pF; Input tr=tf=6 ns; TA -55 to 25°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 15 | ns | VCC 6.0 V; CL=50 pF; Input tr=tf=6 ns; TA 85°C | 3 |
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | | | 18 | ns | VCC 6.0 V; CL=50 pF; Input tr=tf=6 ns; TA 125°C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 75 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA -55 to 25°C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 95 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 85°C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 110 | ns | VCC 2.0 V; CL=50 pF; Input tr=tf=6 ns; TA 125°C | 3 |
## CAD (KiCad official)
- Symbol: `MC74HCU04ADR2G`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mc74hcu04adr2g-etched.step` / `mc74hcu04adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hcu04adr2g.step` / `mc74hcu04adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hcu04a-d.pdf) (9 pp, sha256 `e154ad67b07920fc`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed (audit)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hcu04adr2g-datasheet.pdf)