MC74HCT86ADR2G

{
  "slug": "mc74hct86adr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "mc74hct86adr2g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "mc74hct86adr2g.kicad_sym",
    "mc74hct86adr2g.kicad_mod",
    "mc74hct86adr2g.glb",
    "mc74hct86adr2g.step",
    "mc74hct86adr2g.lbr",
    "docs/hero.png",
    "docs/mc74hct86adr2g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "mc74hct86adr2g-hero.glb",
    "mc74hct86adr2g-hero.overlay.json",
    "mc74hct86adr2g-etched.glb"
  ],
  "component": {
    "mpn": "MC74HCT86ADR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588930086976294912",
    "parts": {
      "symbol": "mc74hct86adr2g.kicad_sym",
      "footprint": "mc74hct86adr2g.kicad_mod",
      "model_3d": "mc74hct86adr2g-hero.glb",
      "model_3d_plain": "mc74hct86adr2g-etched.glb",
      "model_3d_step": "mc74hct86adr2g-etched.step",
      "model_3d_step_plain": "mc74hct86adr2g.step",
      "lbr": "mc74hct86adr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C904085"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T16:58:53Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "A1",
        "type": "input",
        "description": "Input A of gate 1; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "2",
        "name": "B1",
        "type": "input",
        "description": "Input B of gate 1; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "3",
        "name": "Y1",
        "type": "output",
        "description": "Output Y1 of gate 1 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused."
      },
      {
        "number": "4",
        "name": "A2",
        "type": "input",
        "description": "Input A of gate 2; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "5",
        "name": "B2",
        "type": "input",
        "description": "Input B of gate 2; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "6",
        "name": "Y2",
        "type": "output",
        "description": "Output Y2 of gate 2 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for all voltages; DC supply voltage and input/output voltages are referenced to this pin."
      },
      {
        "number": "8",
        "name": "Y3",
        "type": "output",
        "description": "Output Y3 of gate 3 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused."
      },
      {
        "number": "9",
        "name": "A3",
        "type": "input",
        "description": "Input A of gate 3; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "10",
        "name": "B3",
        "type": "input",
        "description": "Input B of gate 3; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "11",
        "name": "Y4",
        "type": "output",
        "description": "Output Y4 of gate 4 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused."
      },
      {
        "number": "12",
        "name": "A4",
        "type": "input",
        "description": "Input A of gate 4; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "13",
        "name": "B4",
        "type": "input",
        "description": "Input B of gate 4; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC)."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply; the DC supply voltage range is 2.0 to 6.0 V referenced to GND."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The PIN ASSIGNMENT block on page 1 is extracted as scrambled number and name lists with no clear pin"
        ],
        "pages_sent": 8,
        "cost_usd": 0.0486,
        "at": "2026-10-18T16:58:38"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588930086976294912",
        "pages": 8,
        "sha256": "05930acff5aa4a54",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "mc74hct86adr2g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "mc74hct86adr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "c4e346c2f04574a9ef1f54691efcb98cdd70753d10c19c8253d7f08a402a75be",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}