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MC74HCT86ADR2G

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onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74HCT86ADR2G

onsemi · Logic Gates · SOIC-14

MC74HCT86ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input A of gate 1; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
2 B1 input Input B of gate 1; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
3 Y1 output Output Y1 of gate 1 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused.
4 A2 input Input A of gate 2; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
5 B2 input Input B of gate 2; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
6 Y2 output Output Y2 of gate 2 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused.
7 GND power_in Ground reference for all voltages; DC supply voltage and input/output voltages are referenced to this pin.
8 Y3 output Output Y3 of gate 3 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused.
9 A3 input Input A of gate 3; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
10 B3 input Input B of gate 3; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
11 Y4 output Output Y4 of gate 4 (Y = A XOR B); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL, and must be left open if unused.
12 A4 input Input A of gate 4; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
13 B4 input Input B of gate 4; inputs must stay within GND to VCC and unused inputs must be tied to a valid logic level (GND or VCC).
14 VCC power_in Positive supply; the DC supply voltage range is 2.0 to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC 2 6 V 2
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V 2
Operating Temperature, All Package Types TA -55 125 °C 2
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V (Figure 1) 2
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V (Figure 1) 2
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V (Figure 1) 2
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V 2
DC Input Voltage (Referenced to GND) Vin -0.5 V 2
DC Output Voltage (Referenced to GND) Vout -0.5 V 2
DC Input Current, per Pin Iin -20 20 mA 2
DC Output Current, per Pin Iout -25 25 mA 2
DC Supply Current, VCC and GND Pins ICC -50 50 mA 2
Power Dissipation in Still Air, SOIC Package PD 500 mW SOIC package, still air 2
Storage Temperature Tstg -65 150 °C 2
Lead Temperature TL 260 °C 1 mm from case for 10 seconds (Plastic DIP, SOIC or TSSOP Package) 2
Minimum High-Level Input Voltage VIH 2 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5 to 5.5 V; −55 to 25°C 3
Maximum Low-Level Input Voltage VIL 0.8 V Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5 to 5.5 V; −55 to 25°C 3
Minimum High-Level Output Voltage VOH 4.4 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; −55 to 25°C 3
Minimum High-Level Output Voltage VOH 5.4 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 5.5 V; −55 to 25°C 3
Minimum High-Level Output Voltage VOH 3.98 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; −55 to 25°C 3
Minimum High-Level Output Voltage VOH 3.84 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; ≤85°C 3
Minimum High-Level Output Voltage VOH 3.7 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; ≤125°C 3
Maximum Low-Level Output Voltage VOL 0.1 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; −55 to 25°C 3
Maximum Low-Level Output Voltage VOL 0.26 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; −55 to 25°C 3
Maximum Low-Level Output Voltage VOL 0.33 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; ≤85°C 3
Maximum Low-Level Output Voltage VOL 0.4 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; ≤125°C 3
Maximum Input Leakage Current Iin -0.1 0.1 µA Vin = VCC or GND; VCC 5.5 V; −55 to 25°C 3
Maximum Input Leakage Current Iin -1 1 µA Vin = VCC or GND; VCC 5.5 V; ≤85°C 3
Maximum Quiescent Supply Current (per Package) ICC 1 µA Vin = VCC or GND; Iout = 0 µA; VCC 5.5 V; −55 to 25°C 3
Maximum Quiescent Supply Current (per Package) ICC 10 µA Vin = VCC or GND; Iout = 0 µA; VCC 5.5 V; ≤85°C 3
Maximum Quiescent Supply Current (per Package) ICC 40 µA Vin = VCC or GND; Iout = 0 µA; VCC 5.5 V; ≤125°C 3
Maximum Propagation Delay, Input A or B to Output Y tPLH 20 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); −55 to 25°C 3
Maximum Propagation Delay, Input A or B to Output Y tPLH 25 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); ≤85°C 3
Maximum Propagation Delay, Input A or B to Output Y tPLH 31 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); ≤125°C 3
Maximum Propagation Delay, Input A or B to Output Y tPHL 17 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); −55 to 25°C 3
Maximum Propagation Delay, Input A or B to Output Y tPHL 21 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); ≤85°C 3
Maximum Propagation Delay, Input A or B to Output Y tPHL 26 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); ≤125°C 3
Maximum Output Transition Time, Any Output tTLH, tTHL 15 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); −55 to 25°C 3
Maximum Output Transition Time, Any Output tTLH, tTHL 19 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); ≤85°C 3
Maximum Output Transition Time, Any Output tTLH, tTHL 22 ns CL = 50 pF, tr = tf = 6 ns, VCC = 5.0 V ±10% (Figures 1 and 2); ≤125°C 3
Maximum Input Capacitance Cin 10 pF 3

CAD (KiCad official)

  • Symbol: MC74HCT86ADR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74hct86adr2g-etched.step / mc74hct86adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hct86adr2g.step / mc74hct86adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 05930acff5aa4a54, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF