MC74HCT595ADR2G

{
  "slug": "mc74hct595adr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "logic",
    "mc74hct595adr2g",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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  "component": {
    "mpn": "MC74HCT595ADR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884671190589440",
    "parts": {
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      "lbr": "mc74hct595adr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C457785"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T21:54:30Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference; all voltage ratings and inputs are referenced to GND."
      },
      {
        "number": "9",
        "name": "SQH",
        "type": "output",
        "description": "Noninverted serial data output from the eighth stage of the 8-bit shift register; this output has no three-state capability."
      },
      {
        "number": "10",
        "name": "RESET",
        "type": "input",
        "description": "Active-low asynchronous reset of the shift register only; a low resets the shift register and does not affect the 8-bit latch."
      },
      {
        "number": "11",
        "name": "SHIFT CLOCK",
        "type": "input",
        "description": "Shift register clock; a low-to-high transition shifts the data at the serial input into the 8-bit shift register."
      },
      {
        "number": "12",
        "name": "LATCH CLOCK",
        "type": "input",
        "description": "Storage latch clock; a low-to-high transition latches the shift register data into the output latch."
      },
      {
        "number": "13",
        "name": "OUTPUT ENABLE",
        "type": "input",
        "description": "Active-low output enable; a low allows the latch data to appear at QA-QH, a high forces QA-QH into high impedance, and SQH is not affected."
      },
      {
        "number": "14",
        "name": "A",
        "type": "input",
        "description": "Serial data input shifted into the 8-bit serial shift register."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply; recommended DC supply range is 4.5 V to 5.5 V referenced to GND, and the maximum rating is 7.0 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The PIN ASSIGNMENT diagram on page 2 is scrambled in the text extraction. Pin numbers were taken fro; GND (pin 8) and VCC (pin 16) are given in the LOGIC DIAGRAM note on page 2. The page-3 text gives ra"
        ],
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        "cost_usd": 0.0781,
        "at": "2026-10-17T21:53:48"
      },
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        "pages": 11,
        "sha256": "55ae617580f618ca",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "centre_offset_mm": 0.0,
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}