component
MC74HCT595ADR2G
Public Made by Adomby adom
onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HCT595ADR2G
onsemi · Shift Registers · SOIC-16
MC74HCT595ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 2 | QC | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 3 | QD | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 4 | QE | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 5 | QF | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 6 | QG | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 7 | QH | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 8 | GND | power_in | Ground reference; all voltage ratings and inputs are referenced to GND. |
| 9 | SQH | output | Noninverted serial data output from the eighth stage of the 8-bit shift register; this output has no three-state capability. |
| 10 | RESET | input | Active-low asynchronous reset of the shift register only; a low resets the shift register and does not affect the 8-bit latch. |
| 11 | SHIFT CLOCK | input | Shift register clock; a low-to-high transition shifts the data at the serial input into the 8-bit shift register. |
| 12 | LATCH CLOCK | input | Storage latch clock; a low-to-high transition latches the shift register data into the output latch. |
| 13 | OUTPUT ENABLE | input | Active-low output enable; a low allows the latch data to appear at QA-QH, a high forces QA-QH into high impedance, and SQH is not affected. |
| 14 | A | input | Serial data input shifted into the 8-bit serial shift register. |
| 15 | QA | tri_state | Noninverted, 3-state parallel latch output; it is forced to high impedance when Output Enable is high. |
| 16 | VCC | power_in | Positive supply; recommended DC supply range is 4.5 V to 5.5 V referenced to GND, and the maximum rating is 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage (recommended operating) | VCC | 4.5 | 5.5 | V | Referenced to GND | 3 | |
| DC input/output voltage (recommended operating) | Vin, Vout | 0 | V | Referenced to GND; max printed as VCC | 3 | ||
| Operating temperature range, all package types | TA | -55 | 125 | °C | 3 | ||
| Input rise/fall time | tr, tf | 0 | 500 | ns | Figure 1 | 3 | |
| DC supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC input voltage (absolute maximum) | Vin | -0.5 | V | Referenced to GND; max printed as VCC + 0.5 | 3 | ||
| DC output voltage (absolute maximum) | Vout | -0.5 | V | Referenced to GND; max printed as VCC + 0.5 | 3 | ||
| DC input current, per pin | Iin | -20 | 20 | mA | Per pin | 3 | |
| DC output current, per pin | Iout | -35 | 35 | mA | Per pin | 3 | |
| DC supply current, VCC and GND pins | ICC | -75 | 75 | mA | VCC and GND pins | 3 | |
| Power dissipation in still air, SOIC package | PD | 500 | mW | SOIC package, still air | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead temperature | TL | 260 | °C | 1 mm from case for 10 seconds; plastic DIP, SOIC or TSSOP package | 3 | ||
| Power dissipation derating, SOIC package | -7 | mW/°C | From 65 to 125 °C, SOIC package | 3 | |||
| Minimum high-level input voltage | VIH | 2 | V | Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5-5.5 V; 125 °C column (worst of −55 to 125 °C) | 4 | ||
| Maximum low-level input voltage | VIL | 0.8 | V | Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5-5.5 V; 125 °C column (worst of −55 to 125 °C) | 4 | ||
| Minimum high-level output voltage, QA-QH | VOH | 4.4 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; 125 °C column | 4 | ||
| Minimum high-level output voltage, QA-QH | VOH | 3.7 | V | Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; VCC 4.5 V; 125 °C column | 4 | ||
| Maximum low-level output voltage, QA-QH | VOL | 0.1 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; 125 °C column | 4 | ||
| Maximum low-level output voltage, QA-QH | VOL | 0.4 | V | Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; VCC 4.5 V; 125 °C column | 4 | ||
| Minimum high-level output voltage, SQH | VOH | 4.4 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; 125 °C column | 4 | ||
| Minimum high-level output voltage, SQH | VOH | 3.7 | V | Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; 125 °C column | 4 | ||
| Maximum low-level output voltage, SQH | VOL | 0.1 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; 125 °C column | 4 | ||
| Maximum low-level output voltage, SQH | VOL | 0.4 | V | Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; 125 °C column | 4 | ||
| Maximum input leakage current | Iin | -1 | 1 | µA | Vin = VCC or GND; VCC 5.5 V; 125 °C column | 4 | |
| Maximum three-state leakage current, QA-QH | IOZ | -10 | 10 | µA | Output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; VCC 5.5 V; 125 °C column | 4 | |
| Maximum quiescent supply current (per package) | ICC | 160 | µA | Vin = VCC or GND; Iout = 0 A; VCC 5.5 V; 125 °C column | 4 | ||
| Additional quiescent supply current | ICC | 2.9 | mA | Vin = 2.4 V, any one input; Vin = VCC or GND, other inputs; Iout = 0 A; VCC 5.5 V; −55 °C column | 4 | ||
| Maximum clock frequency (50% duty cycle) | fmax | 20 | MHz | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum propagation delay, shift clock to SQH | tPLH, tPHL | 42 | ns | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum propagation delay, reset to SQH | tPHL | 44 | ns | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum propagation delay, latch clock to QA-QH | tPLH, tPHL | 42 | ns | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum propagation delay, output enable to QA-QH (disable) | tPLZ, tPHZ | 45 | ns | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum propagation delay, output enable to QA-QH (enable) | tPZL, tPZH | 41 | ns | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum output transition time, QA-QH | tTLH, tTHL | 18 | ns | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum output transition time, SQH | tTLH, tTHL | 22 | ns | CL = 50 pF; tr = tf = 6.0 ns; VCC 4.5-5.5 V; 125 °C column | 5 | ||
| Maximum input capacitance | Cin | 10 | pF | 5 | |||
| Maximum three-state output capacitance (output in high-impedance state), QA-QH | Cout | 15 | pF | Output in high-impedance state, QA-QH | 5 | ||
| Minimum setup time, serial data input A to shift clock | tsu | 15 | ns | Figure 5; VCC 4.5-5.5 V; tr = tf = 6.0 ns; 125 °C column | 5 | ||
| Minimum setup time, shift clock to latch clock | tsu | 22 | ns | Figure 6; VCC 4.5-5.5 V; tr = tf = 6.0 ns; 125 °C column | 5 | ||
| Minimum hold time, shift clock to serial data input A | th | 5 | ns | Figure 5; VCC 4.5-5.5 V; tr = tf = 6.0 ns | 5 | ||
| Minimum recovery time, reset inactive to shift clock | trec | 15 | ns | Figure 2; VCC 4.5-5.5 V; tr = tf = 6.0 ns; 125 °C column | 5 | ||
| Minimum pulse width, reset | tw | 18 | ns | Figure 2; VCC 4.5-5.5 V; tr = tf = 6.0 ns; 125 °C column | 5 | ||
| Minimum pulse width, shift clock | tw | 15 | ns | Figure 1; VCC 4.5-5.5 V; tr = tf = 6.0 ns; 125 °C column | 5 | ||
| Minimum pulse width, latch clock | tw | 15 | ns | Figure 6; VCC 4.5-5.5 V; tr = tf = 6.0 ns; 125 °C column | 5 |
CAD (KiCad official)
- Symbol:
MC74HCT595ADR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hct595adr2g-etched.step/mc74hct595adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hct595adr2g.step/mc74hct595adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
55ae617580f618ca, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).