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MC74HCT574ADTR2G

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onsemi Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74HCT574ADTR2G

onsemi · Flip Flops · TSSOP-20

MC74HCT574ADTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low Output Enable; when high, all Q outputs are forced to the high-impedance state, and it does not affect the stored flip-flop states.
2 D0 input Data input 0 for the D flip-flop, which is clocked to Q0 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
3 D1 input Data input 1 for the D flip-flop, which is clocked to Q1 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
4 D2 input Data input 2 for the D flip-flop, which is clocked to Q2 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
5 D3 input Data input 3 for the D flip-flop, which is clocked to Q3 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
6 D4 input Data input 4 for the D flip-flop, which is clocked to Q4 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
7 D5 input Data input 5 for the D flip-flop, which is clocked to Q5 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
8 D6 input Data input 6 for the D flip-flop, which is clocked to Q6 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
9 D7 input Data input 7 for the D flip-flop, which is clocked to Q7 on the rising edge of CLOCK; inputs must be held within GND to VCC and unused inputs must be tied to GND or VCC.
10 GND power_in Ground reference (0 V) for all voltages in the device, per the datasheet's voltages-referenced-to-GND convention.
11 CLOCK input Clock input; data meeting setup time is transferred to the outputs on its rising edge.
12 Q7 tri_state Non-inverting 3-state output 7, which drives 15 LSTTL loads and is high-impedance when OE is high.
13 Q6 tri_state Non-inverting 3-state output 6, which drives 15 LSTTL loads and is high-impedance when OE is high.
14 Q5 tri_state Non-inverting 3-state output 5, which drives 15 LSTTL loads and is high-impedance when OE is high.
15 Q4 tri_state Non-inverting 3-state output 4, which drives 15 LSTTL loads and is high-impedance when OE is high.
16 Q3 tri_state Non-inverting 3-state output 3, which drives 15 LSTTL loads and is high-impedance when OE is high.
17 Q2 tri_state Non-inverting 3-state output 2, which drives 15 LSTTL loads and is high-impedance when OE is high.
18 Q1 tri_state Non-inverting 3-state output 1, which drives 15 LSTTL loads and is high-impedance when OE is high.
19 Q0 tri_state Non-inverting 3-state output 0, which drives 15 LSTTL loads and is high-impedance when OE is high.
20 VCC power_in Positive supply; the recommended operating range is 4.5 V to 5.5 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC 4.5 5.5 V Referenced to GND 2
DC Input Voltage, Output Voltage Vin, Vout 0 V Referenced to GND; printed max is VCC 2
Operating Temperature, All Package Types TA -55 125 °C All package types 2
Input Rise and Fall Time tr, tf 0 500 ns Figure 2 2
DC Supply Voltage VCC -0.5 7 V Referenced to GND 2
DC Input Voltage Vin -0.5 V Referenced to GND; printed max is VCC + 0.5 2
DC Output Voltage Vout -0.5 V Referenced to GND; printed max is VCC + 0.5 2
DC Input Current, per Pin Iin -20 20 mA Per pin 2
DC Output Current, per Pin Iout -35 35 mA Per pin 2
DC Supply Current, VCC and GND Pins ICC -75 75 mA VCC and GND pins 2
Storage Temperature Tstg -65 150 °C 2
Minimum High-Level Input Voltage VIH 2 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5 V and 5.5 V; 2.0 V at all temperature ranges 3
Maximum Low-Level Input Voltage VIL 0.8 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5 V and 5.5 V; 0.8 V at all temperature ranges 3
Minimum High-Level Output Voltage VOH 4.4 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 4.5 V; all temperature ranges 3
Minimum High-Level Output Voltage VOH 5.4 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 5.5 V; all temperature ranges 3
Minimum High-Level Output Voltage VOH 3.7 V Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; VCC = 4.5 V; 3.98 V at −55 to 25 °C, 3.84 V at 85 °C, 3.7 V at 125 °C 3
Maximum Low-Level Output Voltage VOL 0.1 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 4.5 V; all temperature ranges 3
Maximum Low-Level Output Voltage VOL 0.4 V Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; VCC = 4.5 V; 0.26 V at −55 to 25 °C, 0.33 V at 85 °C, 0.4 V at 125 °C 3
Maximum Input Leakage Current Iin -1 1 µA Vin = VCC or GND; VCC = 5.5 V; ±0.1 µA at −55 to 25 °C, ±1.0 µA at 85 and 125 °C 3
Maximum Quiescent Supply Current (per Package) ICC 160 µA Vin = VCC or GND; Iout = 0 µA; VCC = 5.5 V; 4.0 µA at −55 to 25 °C, 40 µA at 85 °C 3
Maximum Three-State Leakage Current IOZ -10 µA Vin = VIL or VIH; Vout = VCC or GND; VCC = 5.5 V; printed −0.5 µA at −55 to 25 °C, −5.0 µA at 85 °C, −10 µA at 125 °C 3
Additional Quiescent Supply Current ICC 2.9 mA Vin = 2.4 V any one input; other inputs VCC or GND; Iout = 0 µA; VCC = 5.5 V; 2.9 mA at −55 °C, 2.4 mA at 25 to 125 °C 3
Maximum Input Capacitance Cin 10 pF 3
Maximum Clock Frequency (50% Duty Cycle) fMAX 20 MHz VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns; Figures 2 and 5; 30 MHz at −55 to 25 °C, 24 MHz at 85 °C 3
Maximum Propagation Delay, Clock to Q tPLH, tPHL 45 ns VCC = 5.0 V ±10%, CL = 50 pF; Figures 2 and 5; 30 ns at −55 to 25 °C, 38 ns at 85 °C 3
Maximum Propagation Delay, Output Enable to Q tPLZ, tPHZ 42 ns VCC = 5.0 V ±10%, CL = 50 pF; Figures 3 and 6; 28 ns at −55 to 25 °C, 35 ns at 85 °C 3
Maximum Propagation Delay Time, Output Enable to Q tPZH, tPZL 42 ns VCC = 5.0 V ±10%, CL = 50 pF; Figures 3 and 6; 28 ns at −55 to 25 °C, 35 ns at 85 °C 3
Maximum Output Transition Time, Any Output tTLH, tTHL 18 ns VCC = 5.0 V ±10%, CL = 50 pF; Figures 2, 3 and 5; 12 ns at −55 to 25 °C, 15 ns at 85 °C 3
Minimum Setup Time, Data to Clock tsu 15 ns VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns; Figure 4; 10 ns at −55 to 25 °C, 13 ns at 85 °C 3
Minimum Hold Time, Clock to Data th 5 ns VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns; Figure 4; 5.0 ns at all temperature ranges 3
Minimum Pulse Width, Clock tw 22 ns VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns; Figure 2; 15 ns at −55 to 25 °C, 19 ns at 85 °C 3
Maximum Input Rise and Fall Times tr, tf 500 ns VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns; Figure 2; 500 ns at all temperature ranges 3

CAD (KiCad official)

  • Symbol: MC74HCT574ADTR2G
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: mc74hct574adtr2g-etched.step / mc74hct574adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hct574adtr2g.step / mc74hct574adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 bef4625920f3ada2, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF